f7d8336a2f
This patch is in preparation to enable setting the MachineInstr::MIFlag
flags, i.e. FrameSetup/FrameDestroy, on callee saved register
spill/reload instructions in prologue/epilogue. This eventually helps in
setting the prologue_end and epilogue_begin markers more accurately.
The DWARF Spec in "6.4 Call Frame Information" says:
The code that allocates space on the call frame stack and performs the
save
operation is called the subroutine’s prologue, and the code that
performs
the restore operation and deallocates the frame is called its epilogue.
which means the callee saved register spills and reloads are part of
prologue (a.k.a frame setup) and epilogue (a.k.a frame destruction),
respectively. And, IIUC, LLVM backend uses FrameSetup/FrameDestroy flags
to identify instructions that are part of call frame setup and
destruction.
In the trunk, while most targets consistently set
FrameSetup/FrameDestroy on save/restore call frame information (CFI)
instructions of callee saved registers, they do not consistently set
those flags on the actual callee saved register spill/reload
instructions.
I believe this patch provides a clean mechanism to set
FrameSetup/FrameDestroy flags on the actual callee saved register
spill/reload instructions as needed. And, by having default argument of
MachineInstr::NoFlags for Flags, this patch is a NFC.
With this patch, the targets have to just pass FrameSetup/FrameDestroy
flag to the storeRegToStackSlot/loadRegFromStackSlot calls from the
target derived spillCalleeSavedRegisters and restoreCalleeSavedRegisters
to set those flags on callee saved register spill/reload instructions.
Also, this patch makes it very easy to set the source line information
on callee saved register spill/reload instructions which is needed by
the DwarfDebug.cpp implementation to set prologue_end and epilogue_begin
markers more accurately.
As per DwarfDebug.cpp implementation:
prologue_end is the first known non-DBG_VALUE and non-FrameSetup
location
that marks the beginning of the function body
epilogue_begin is the first FrameDestroy location that has been seen in
the
epilogue basic block
With this patch, the targets have to just do the following to set the
source line information on callee saved register spill/reload
instructions, without hampering the LLVM's efforts to avoid adding
source line information on the artificial code generated by the
compiler.
<Foo>InstrInfo::storeRegToStackSlot() {
...
DebugLoc DL =
Flags & MachineInstr::FrameSetup ? DebugLoc() : MBB.findDebugLoc(I);
...
}
<Foo>InstrInfo::loadRegFromStackSlot() {
...
DebugLoc DL =
Flags & MachineInstr::FrameDestroy ? MBB.findDebugLoc(I) : DebugLoc();
...
}
While I understand this patch would break out-of-tree backend builds, I
think it is in the right direction.
One immediate use case that can benefit from this patch is fixing
#120553 becomes simpler.
238 lines
9.1 KiB
C++
238 lines
9.1 KiB
C++
//===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the TargetInstrInfo class.
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//
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// FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in
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// order for MipsLongBranch pass to work correctly when the code has inline
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// assembly. The returned value doesn't have to be the asm instruction's exact
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// size in bytes; MipsLongBranch only expects it to be the correct upper bound.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
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#define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
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#include "MCTargetDesc/MipsMCTargetDesc.h"
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#include "Mips.h"
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#include "MipsRegisterInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include <cstdint>
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#define GET_INSTRINFO_HEADER
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#include "MipsGenInstrInfo.inc"
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namespace llvm {
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class MachineInstr;
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class MachineOperand;
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class MipsSubtarget;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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class MipsInstrInfo : public MipsGenInstrInfo {
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virtual void anchor();
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protected:
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const MipsSubtarget &Subtarget;
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unsigned UncondBrOpc;
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public:
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enum BranchType {
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BT_None, // Couldn't analyze branch.
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BT_NoBranch, // No branches found.
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BT_Uncond, // One unconditional branch.
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BT_Cond, // One conditional branch.
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BT_CondUncond, // A conditional branch followed by an unconditional branch.
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BT_Indirect // One indirct branch.
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};
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explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc);
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static const MipsInstrInfo *create(MipsSubtarget &STI);
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/// Branch Analysis
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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BranchType analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify,
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SmallVectorImpl<MachineInstr *> &BranchInstrs) const;
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/// Determine the opcode of a non-delay slot form for a branch if one exists.
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unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const;
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/// Determine if the branch target is in range.
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bool isBranchOffsetInRange(unsigned BranchOpc,
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int64_t BrOffset) const override;
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bool SafeAfterMflo(const MachineInstr &MI) const;
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/// Predicate to determine if an instruction can go in a forbidden slot.
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bool SafeInForbiddenSlot(const MachineInstr &MI) const;
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/// Predicate to determine if an instruction can go in an FPU delay slot.
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bool SafeInFPUDelaySlot(const MachineInstr &MIInSlot,
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const MachineInstr &FPUMI) const;
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/// Predicate to determine if an instruction can go in a load delay slot.
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bool SafeInLoadDelaySlot(const MachineInstr &MIInSlot,
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const MachineInstr &LoadMI) const;
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bool IsMfloOrMfhi(const MachineInstr &MI) const;
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/// Predicate to determine if an instruction has a forbidden slot.
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bool HasForbiddenSlot(const MachineInstr &MI) const;
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/// Predicate to determine if an instruction has an FPU delay slot.
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bool HasFPUDelaySlot(const MachineInstr &MI) const;
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/// Predicate to determine if an instruction has a load delay slot.
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bool HasLoadDelaySlot(const MachineInstr &MI) const;
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/// Insert nop instruction when hazard condition is found
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void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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/// Insert an ISA appropriate `nop`.
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// FIXME: Add support for MIPS16e.
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MachineInstrBuilder insertNop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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DebugLoc DL) const;
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
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virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
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virtual bool isBranchWithImm(unsigned Opc) const {
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return false;
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}
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/// Return the number of bytes of code the specified instruction may be.
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unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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void storeRegToStackSlot(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
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bool isKill, int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI, Register VReg,
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MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override {
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storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0, Flags);
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}
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void loadRegFromStackSlot(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI, Register VReg,
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MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override {
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loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0, Flags);
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}
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virtual void
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storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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Register SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
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int64_t Offset,
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MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const = 0;
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virtual void loadRegFromStack(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
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int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI, int64_t Offset,
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MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const = 0;
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virtual void adjustStackPtr(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const = 0;
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/// Create an instruction which has the same operands and memory operands
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/// as MI but has a new opcode.
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MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
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MachineBasicBlock::iterator I) const;
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bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const override;
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/// Perform target specific instruction verification.
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bool verifyInstruction(const MachineInstr &MI,
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StringRef &ErrInfo) const override;
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std::pair<unsigned, unsigned>
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decomposeMachineOperandsTargetFlags(unsigned TF) const override;
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ArrayRef<std::pair<unsigned, const char *>>
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getSerializableDirectMachineOperandTargetFlags() const override;
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std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
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Register Reg) const override;
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std::optional<ParamLoadedValue>
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describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
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protected:
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bool isZeroImm(const MachineOperand &op) const;
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MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI,
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MachineMemOperand::Flags Flags) const;
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private:
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virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
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void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
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MachineBasicBlock *&BB,
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SmallVectorImpl<MachineOperand> &Cond) const;
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void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
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};
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/// Create MipsInstrInfo objects.
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const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI);
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const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI);
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namespace Mips {
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// Mask assignments for floating-point.
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enum FClassMask {
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FClassMaskSignalingNaN = 1 << 0,
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FClassMaskQuietNaN = 1 << 1,
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FClassMaskNegativeInfinity = 1 << 2,
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FClassMaskNegativeNormal = 1 << 3,
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FClassMaskNegativeSubnormal = 1 << 4,
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FClassMaskNegativeZero = 1 << 5,
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FClassMaskPositiveInfinity = 1 << 6,
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FClassMaskPositiveNormal = 1 << 7,
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FClassMaskPositiveSubnormal = 1 << 8,
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FClassMaskPositiveZero = 1 << 9
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};
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} // namespace Mips
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
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