David Green b9622e84b4 [TTI][AArch64] Detect OperandInfo from scalable splats. (#122469) ...

Pulled out of #122236, this allows Splats constants to be recognized by
getOperandInfo, allowing "better" costs for instructions like divides by
constants to be produced (which are expanded into mul+add+shift). Some
of the costs are not very accurate yet, but the comparison of scalar vs
fixed-width vs scalable for the same div can become more accurate,
especially with patches like #122236.

2025-02-21 10:41:44 +00:00

..

abs.ll

[RISCV][TTI] Implement cost of intrinsic abs with LMUL (#115813)

2024-11-25 17:35:58 +08:00

active_lane_mask.ll

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arith-fp.ll

[RISCV] Add cost model for fma (#126076)

2025-02-10 10:11:28 -03:00

arith-int.ll

[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)

2024-11-06 11:53:33 +00:00

cast-half.ll

[RISCV] Remove {s,u}int_to_fp custom op action for f16/bf16 (#111471)

2024-10-10 14:40:24 +01:00

cast.ll

[RISCV] Fix vp-intrinsics args in cost model tests. NFC (#112463)

2024-10-16 12:57:43 +08:00

cmp-select.ll

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cmp.ll

[RISCV] Fix vp-intrinsics args in cost model tests. NFC (#112463)

2024-10-16 12:57:43 +08:00

cttz_elts.ll

[RISCV][CostModel] Correct the cost of some reductions (#118072)

2024-12-04 17:26:54 +08:00

extractelement.ll

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fca-load-store.ll

[RISCV] Remove -riscv-v-vector-bits-min from cost model tests. NFC

2024-09-20 15:02:42 +08:00

fixed-vector-gather.ll

[RISCV] Lower fixed-length mgather/mscatter for zvfhmin/zvfbfmin (#114945)

2024-11-06 10:33:06 +08:00

fixed-vector-insert-subvector.ll

[RISCV][TTI] Recognize CONCAT_VECTORS if a shufflevector mask is multiple insert subvector. (#111459)

2024-10-18 20:16:56 +07:00

fixed-vector-scatter.ll

[RISCV] Lower fixed-length mgather/mscatter for zvfhmin/zvfbfmin (#114945)

2024-11-06 10:33:06 +08:00

fp-min-max-abs.ll

[RISCV][CostModel] Add cost for fabs/fsqrt of type bf16/f16 (#118608)

2025-01-10 17:22:51 +08:00

fp-sqrt-pow.ll

[RISCV][CostModel] Add cost for fabs/fsqrt of type bf16/f16 (#118608)

2025-01-10 17:22:51 +08:00

fp-trig-log-exp.ll

[Test] Rename the test function name suffix. NFC (#114504)

2024-11-01 13:49:34 +08:00

fround.ll

[Test] Rename the test function name suffix. NFC (#114504)

2024-11-01 13:49:34 +08:00

gep-zero-indices.ll

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gep.ll

[TTI][CostModel] Add cost modeling for expandload and compressstore intrinsics (#122882)

2025-02-04 15:08:30 +03:00

insertelement.ll

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int-bit-manip.ll

[TTI][RISCV] Implement cost of some intrinsics with LMUL (#117874)

2024-12-03 10:17:52 +08:00

int-min-max.ll

[Test] Rename the test function name suffix. NFC (#114504)

2024-11-01 13:49:34 +08:00

int-sat-math.ll

[TTI][RISCV] Implement cost of some intrinsics with LMUL (#117874)

2024-12-03 10:17:52 +08:00

lit.local.cfg

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load-to-trunc.ll

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logicalop.ll

[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)

2024-11-06 11:53:33 +00:00

masked_ldst.ll

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phi-const.ll

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reduce-add.ll

[RISCV] Remove -riscv-v-vector-bits-min from cost model tests. NFC

2024-09-20 15:02:42 +08:00

reduce-and-i1.ll

[RISCV] Fix the cost of llvm.vector.reduce.and (#119160)

2025-01-10 10:10:42 +08:00

reduce-and.ll

[RISCV] Fix the cost of llvm.vector.reduce.and (#119160)

2025-01-10 10:10:42 +08:00

reduce-fadd.ll

[RISCV] Cost ordered bf16/f16 w/ zvfhmin reductions as invalid (#114250)

2024-10-31 23:36:09 +08:00

reduce-fmaximum.ll

[RISCV] Remove -riscv-v-vector-bits-min from cost model tests. NFC

2024-09-20 15:02:42 +08:00

reduce-fminimum.ll

[RISCV] Remove -riscv-v-vector-bits-min from cost model tests. NFC

2024-09-20 15:02:42 +08:00

reduce-fmul.ll

[RISCV] Add cost model tests for scalable FP reductions. NFC

2024-10-29 23:58:06 +02:00

reduce-max.ll

[RISCV] Fix the cost of llvm.vector.reduce.and (#119160)

2025-01-10 10:10:42 +08:00

reduce-min.ll

[RISCV] Fix the cost of llvm.vector.reduce.and (#119160)

2025-01-10 10:10:42 +08:00

reduce-or.ll

[RISCV][CostModel] Correct the cost of some reductions (#118072)

2024-12-04 17:26:54 +08:00

reduce-scalable-fp.ll

[RISCV][CostModel] Correct the cost of some reductions (#118072)

2024-12-04 17:26:54 +08:00

reduce-scalable-int.ll

[RISCV][CostModel] Correct the cost of some reductions (#118072)

2024-12-04 17:26:54 +08:00

reduce-xor.ll

[RISCV] Remove -riscv-v-vector-bits-min from cost model tests. NFC

2024-09-20 15:02:42 +08:00

rvv-cmp.ll

[RISCV][NFC] precommit test for fcmp with f16

2025-01-03 01:45:27 -08:00

rvv-expandload-compressstore.ll

[TTI][CostModel] Add cost modeling for expandload and compressstore intrinsics (#122882)

2025-02-04 15:08:30 +03:00

rvv-extractelement.ll

[RISCV][TTI] Model the cost of insert/extractelt when the vector split into multiple register group and idx exceed single group. (#118401)

2024-12-12 09:26:19 +08:00

rvv-fcmp-f16.ll

[RISCV][NFC] precommit test for fcmp with f16

2025-01-03 01:45:27 -08:00

rvv-insertelement.ll

[RISCV][TTI] Model the cost of insert/extractelt when the vector split into multiple register group and idx exceed single group. (#118401)

2024-12-12 09:26:19 +08:00

rvv-load-store.ll

[TTI][AArch64] Detect OperandInfo from scalable splats. (#122469)

2025-02-21 10:41:44 +00:00

rvv-phi-const.ll

[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)

2024-11-06 11:53:33 +00:00

rvv-select.ll

[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)

2024-11-06 11:53:33 +00:00

rvv-shuffle.ll

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rvv-vectorextract.ll

…

rvv-vectorinsert.ll

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scalable-gather.ll

[RISCV] Lower fixed-length mgather/mscatter for zvfhmin/zvfbfmin (#114945)

2024-11-06 10:33:06 +08:00

scalable-scatter.ll

[RISCV] Lower fixed-length mgather/mscatter for zvfhmin/zvfbfmin (#114945)

2024-11-06 10:33:06 +08:00

shuffle-broadcast.ll

[RISCV] Add zvfhmin cost model test coverage. NFC

2024-09-12 18:41:47 +08:00

shuffle-exact-vlen.ll

[RISCV][TTI]Use processShuffleMasks for cost estimations/actual per-register shuffles

2025-01-29 07:18:55 -05:00

shuffle-extract_subvector.ll

[RISCV][TTI]Use processShuffleMasks for cost estimations/actual per-register shuffles

2025-01-29 07:18:55 -05:00

shuffle-insert_subvector.ll

[RISCV][TTI]Use processShuffleMasks for cost estimations/actual per-register shuffles

2025-01-29 07:18:55 -05:00

shuffle-insert.ll

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shuffle-interleave.ll

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shuffle-permute.ll

[RISCV] Add zvfhmin cost model test coverage. NFC

2024-09-12 18:41:47 +08:00

shuffle-reverse.ll

[RISCV] Remove -riscv-v-vector-bits-min from cost model tests. NFC

2024-09-20 15:02:42 +08:00

shuffle-select.ll

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shuffle-transpose.ll

[RISCV] Remove -riscv-v-vector-bits-min from cost model tests. NFC

2024-09-20 15:02:42 +08:00

splice.ll

[RISCV] Lower vector_splice on zvfhmin/zvfbfmin (#112579)

2024-10-16 21:40:18 +01:00

stepvector.ll

Move stepvector intrinsic out of experimental namespace (#98043)

2024-08-28 12:48:20 +01:00

vector-cost-without-v.ll

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vp-intrinsics.ll

[RISCV][TTI] Fix test fails for #124221 NFC. (#125792)

2025-02-05 08:49:41 +08:00