Philip Reames 059722da5e Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit. ...

This reverts commit 9cc8442a2b.
This reverts commit 859c871184.

A performance regression was reported on the original review.  There appears
to have been an unexpected interaction here.  Reverting during investigation.

2025-02-13 09:57:33 -08:00

..

instruction-select

[RISCV] Select mask operands as virtual registers and eliminate uses of vmv0 (#125026)

2025-02-12 12:06:55 +08:00

irtranslator

[RISCV][GISel] Fallback in LowerCall for byval arguments. (#119251)

2024-12-09 14:22:05 -08:00

legalizer

[AArch64][GlobalISel] Add disjoint handling for add_and_or_is_add. (#123594)

2025-02-02 21:01:49 +00:00

regbankselect

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rvv

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add-imm.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.

2025-02-13 09:57:33 -08:00

alu-roundtrip-rv64.ll

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alu-roundtrip.ll

[RISCV] GISel custom lowering for G_ADD/G_SUB (#121587)

2025-01-07 18:53:10 -08:00

atomic-fence.ll

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atomic-load-store.ll

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bitmanip.ll

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calllowering-ret.ll

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combine-neg-abs.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.

2025-02-13 09:57:33 -08:00

combine.ll

[RISCV] Porting hasAllNBitUsers to RISCV GISel for instruction select (#125795)

2025-02-06 11:57:52 -05:00

combine.mir

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constantpool.ll

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constbarrier-rv32.ll

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constbarrier-rv64.ll

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div-by-constant.ll

[RISCV] Porting hasAllNBitUsers to RISCV GISel for instruction select (#125795)

2025-02-06 11:57:52 -05:00

double-arith.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.

2025-02-13 09:57:33 -08:00

double-convert.ll

[GISel][RISCV] Use isSExtCheaperThanZExt when widening G_ICMP. (#120032)

2024-12-15 22:55:58 -08:00

double-fcmp.ll

[GISel][RISCV] Use isSExtCheaperThanZExt when widening G_ICMP. (#120032)

2024-12-15 22:55:58 -08:00

double-intrinsics.ll

[RISCV][GISel] Added GISelPredicateCodes to LeadingOnes*Mask (#119886)

2024-12-13 14:23:16 -08:00

double-zfa.ll

[RISCV][GISel] Support G_MERGE_VALUES/G_UNMERGE_VALUES with Zfa. (#120379)

2025-01-07 07:50:50 -08:00

float-arith.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.

2025-02-13 09:57:33 -08:00

float-convert.ll

[GISel][RISCV] Use isSExtCheaperThanZExt when widening G_ICMP. (#120032)

2024-12-15 22:55:58 -08:00

float-fclass.ll

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float-fcmp.ll

[GISel][RISCV] Use isSExtCheaperThanZExt when widening G_ICMP. (#120032)

2024-12-15 22:55:58 -08:00

float-intrinsics.ll

[GISel][RISCV] Use isSExtCheaperThanZExt when widening G_ICMP. (#120032)

2024-12-15 22:55:58 -08:00

float-zfa.ll

[RISCV][GISel] Add Zfa FP legalization and full tests for 9 insn (#118723)

2024-12-05 12:49:07 -08:00

fp128.ll

[RISCV][GISel] Add legalization for more fp128 libcalls.

2024-12-16 23:39:09 -08:00

fpr-gpr-copy-rv32.ll

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fpr-gpr-copy-rv64.ll

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freeze.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.

2025-02-13 09:57:33 -08:00

gisel-commandline-option.ll

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half-zfa.ll

[RISCV][GISel] Add Zfa FP legalization and full tests for 9 insn (#118723)

2024-12-05 12:49:07 -08:00

iabs.ll

[RISCV] GISel custom lowering for G_ADD/G_SUB (#121587)

2025-01-07 18:53:10 -08:00

irtranslator-calllowering.ll

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jumptable.ll

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knownbits-copy-crash.mir

[GISel] Teach computeKnownBitsImpl to handle COPY instructions that change bit width. (#118924)

2024-12-06 21:31:19 -08:00

legalizer-info-validation.mir

[RISCV] GISel custom lowering for G_ADD/G_SUB (#121587)

2025-01-07 18:53:10 -08:00

libcalls.ll

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phi.ll

[RISCV][GISel] Allow s32 G_PHI for RV64 to support f32 phis.

2024-12-06 11:53:57 -08:00

riscv-unsupported.ll

[RISCV][GISel] Fallback in LowerCall for byval arguments. (#119251)

2024-12-09 14:22:05 -08:00

rotl-rotr.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.

2025-02-13 09:57:33 -08:00

rv32zba.ll

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rv32zbb-zbkb.ll

[RISCV][GISel] Port TrailingOnesMask PatLeaf. (#119427)

2024-12-10 22:17:52 -08:00

rv32zbb.ll

[RISCV][GISel] Port TrailingOnesMask PatLeaf. (#119427)

2024-12-10 22:17:52 -08:00

rv32zbkb.ll

[RISCV][GISel] Port TrailingOnesMask PatLeaf. (#119427)

2024-12-10 22:17:52 -08:00

rv64-double-convert.ll

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rv64-float-convert.ll

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rv64zba.ll

[RISCV][GISel] Added GISelPredicateCodes to LeadingOnes*Mask (#119886)

2024-12-13 14:23:16 -08:00

rv64zbb-zbkb.ll

[RISCV] Porting hasAllNBitUsers to RISCV GISel for instruction select (#125795)

2025-02-06 11:57:52 -05:00

rv64zbb.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.

2025-02-13 09:57:33 -08:00

rv64zbkb.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.

2025-02-13 09:57:33 -08:00

scalablevec-combiner-crash.ll

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scmp.ll

[RISCV] GISel custom lowering for G_ADD/G_SUB (#121587)

2025-01-07 18:53:10 -08:00

shift.ll

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shifts.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.

2025-02-13 09:57:33 -08:00

stacksave-stackrestore.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.

2025-02-13 09:57:33 -08:00

ucmp.ll

[RISCV] GISel custom lowering for G_ADD/G_SUB (#121587)

2025-01-07 18:53:10 -08:00

vararg.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.

2025-02-13 09:57:33 -08:00

wide-scalar-shift-by-byte-multiple-legalization.ll

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.

2025-02-13 09:57:33 -08:00