8424bf207e
This patch adds support for the next-generation arch15 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Detection of arch15 as host processor. - Assembler/disassembler support for new instructions. - Exploitation of new instructions for code generation. - New vector (signed|unsigned|bool) __int128 data types. - New LLVM intrinsics for certain new instructions. - Support for low-level builtins mapped to new LLVM intrinsics. - New high-level intrinsics in vecintrin.h. - Indicate support by defining __VEC__ == 10305. Note: No currently available Z system supports the arch15 architecture. Once new systems become available, the official system name will be added as supported -march name.
29 lines
755 B
LLVM
29 lines
755 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; Test bit deposit / extract intrinsics
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
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declare i64 @llvm.s390.bdepg(i64, i64)
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declare i64 @llvm.s390.bextg(i64, i64)
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; BDEPG.
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define i64 @test_bdepg(i64 %a, i64 %b) {
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; CHECK-LABEL: test_bdepg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bdepg %r2, %r2, %r3
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; CHECK-NEXT: br %r14
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%res = call i64 @llvm.s390.bdepg(i64 %a, i64 %b)
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ret i64 %res
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}
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; BEXTG.
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define i64 @test_bextg(i64 %a, i64 %b) {
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; CHECK-LABEL: test_bextg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bextg %r2, %r2, %r3
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; CHECK-NEXT: br %r14
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%res = call i64 @llvm.s390.bextg(i64 %a, i64 %b)
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ret i64 %res
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}
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