07d284d4eb
Adds cost estimation for the variants of the permutations of the scalar
values, used in gather nodes. Currently, SLP just unconditionally emits
shuffles for the reused buildvectors, but in some cases better to leave
them as buildvectors rather than shuffles, if the cost of such
buildvectors is better.
X86, AVX512, -O3+LTO
Metric: size..text
Program size..text
results results0 diff
test-suite :: External/SPEC/CINT2006/445.gobmk/445.gobmk.test 912998.00 913238.00 0.0%
test-suite :: MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame.test 203070.00 203102.00 0.0%
test-suite :: External/SPEC/CFP2017speed/638.imagick_s/638.imagick_s.test 1396320.00 1396448.00 0.0%
test-suite :: External/SPEC/CFP2017rate/538.imagick_r/538.imagick_r.test 1396320.00 1396448.00 0.0%
test-suite :: MultiSource/Benchmarks/Bullet/bullet.test 309790.00 309678.00 -0.0%
test-suite :: External/SPEC/CFP2017rate/526.blender_r/526.blender_r.test 12477607.00 12470807.00 -0.1%
CINT2006/445.gobmk - extra code vectorized
MiBench/consumer-lame - small variations
CFP2017speed/638.imagick_s
CFP2017rate/538.imagick_r - extra vectorized code
Benchmarks/Bullet - extra code vectorized
CFP2017rate/526.blender_r - extra vector code
RISC-V, sifive-p670, -O3+LTO
CFP2006/433.milc - regressions, should be fixed by https://github.com/llvm/llvm-project/pull/115173
CFP2006/453.povray - extra vectorized code
CFP2017rate/508.namd_r - better vector code
CFP2017rate/510.parest_r - extra vectorized code
SPEC/CFP2017rate - extra/better vector code
CFP2017rate/526.blender_r - extra vectorized code
CFP2017rate/538.imagick_r - extra vectorized code
CINT2006/403.gcc - extra vectorized code
CINT2006/445.gobmk - extra vectorized code
CINT2006/464.h264ref - extra vectorized code
CINT2006/483.xalancbmk - small variations
CINT2017rate/525.x264_r - better vectorization
Reviewers: RKSimon
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/115201
112 lines
5.9 KiB
LLVM
112 lines
5.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -mtriple=arm64-apple-macosx11.0.0 -passes=slp-vectorizer -S < %s | FileCheck %s
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; Test case reported on D134605 where the vectorization was causing a slowdown due to an underestimation in the cost of the extractions.
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; NOTE: cost of shuffle <4 x float>, <4 x float>, <2 x i32> <i32 2, i32 5> is 12!
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define fastcc i64 @zot(float %arg, float %arg1, float %arg2, float %arg3, float %arg4, ptr %arg5, i1 %arg6, i1 %arg7, i1 %arg8) {
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; CHECK-LABEL: @zot(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[VAL9:%.*]] = fmul fast float 0.000000e+00, [[ARG:%.*]]
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; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> <float 0.000000e+00, float poison, float poison, float poison>, float [[ARG]], i32 1
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[ARG3:%.*]], i32 2
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; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
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; CHECK-NEXT: [[TMP3:%.*]] = fmul fast <4 x float> <float 0.000000e+00, float 0.000000e+00, float 1.000000e+00, float 1.000000e+00>, [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x float> <float poison, float 0.000000e+00>, float [[ARG3]], i32 0
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; CHECK-NEXT: [[TMP5:%.*]] = fadd fast <2 x float> [[TMP4]], <float 1.000000e+00, float 0.000000e+00>
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; CHECK-NEXT: [[TMP6:%.*]] = call <4 x float> @llvm.vector.insert.v4f32.v2f32(<4 x float> [[TMP2]], <2 x float> [[TMP5]], i64 0)
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; CHECK-NEXT: [[TMP7:%.*]] = fadd fast <4 x float> [[TMP6]], <float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
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; CHECK-NEXT: br i1 [[ARG6:%.*]], label [[BB18:%.*]], label [[BB57:%.*]]
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; CHECK: bb18:
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; CHECK-NEXT: [[TMP8:%.*]] = phi <4 x float> [ [[TMP7]], [[BB:%.*]] ]
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; CHECK-NEXT: [[VAL16:%.*]] = extractelement <4 x float> [[TMP7]], i32 2
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; CHECK-NEXT: [[VAL23:%.*]] = fmul fast float [[VAL16]], 2.000000e+00
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; CHECK-NEXT: [[VAL17:%.*]] = extractelement <4 x float> [[TMP7]], i32 3
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; CHECK-NEXT: [[VAL24:%.*]] = fmul fast float [[VAL17]], 3.000000e+00
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; CHECK-NEXT: br i1 [[ARG7:%.*]], label [[BB25:%.*]], label [[BB57]]
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; CHECK: bb25:
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; CHECK-NEXT: [[TMP11:%.*]] = phi <4 x float> [ [[TMP8]], [[BB18]] ]
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; CHECK-NEXT: br label [[BB30:%.*]]
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; CHECK: bb30:
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; CHECK-NEXT: [[VAL31:%.*]] = phi float [ [[VAL55:%.*]], [[BB30]] ], [ 0.000000e+00, [[BB25]] ]
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; CHECK-NEXT: [[VAL32:%.*]] = phi float [ [[VAL9]], [[BB30]] ], [ 0.000000e+00, [[BB25]] ]
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; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i8>, ptr [[ARG5:%.*]], align 1
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; CHECK-NEXT: [[TMP13:%.*]] = uitofp <4 x i8> [[TMP12]] to <4 x float>
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; CHECK-NEXT: [[TMP14:%.*]] = fsub fast <4 x float> [[TMP13]], [[TMP3]]
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; CHECK-NEXT: [[TMP15:%.*]] = fmul fast <4 x float> [[TMP14]], [[TMP11]]
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; CHECK-NEXT: [[VAL54:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[TMP15]])
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; CHECK-NEXT: [[VAL55]] = tail call fast float @llvm.minnum.f32(float [[VAL31]], float [[ARG1:%.*]])
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; CHECK-NEXT: [[VAL56:%.*]] = tail call fast float @llvm.maxnum.f32(float [[ARG2:%.*]], float [[VAL54]])
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; CHECK-NEXT: call void @ham(float [[VAL55]], float [[VAL56]])
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; CHECK-NEXT: br i1 [[ARG8:%.*]], label [[BB30]], label [[BB57]]
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; CHECK: bb57:
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; CHECK-NEXT: ret i64 0
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;
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bb:
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%val = fmul fast float 0.000000e+00, 0.000000e+00
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%val9 = fmul fast float 0.000000e+00, %arg
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%val10 = fmul fast float %arg3, 1.000000e+00
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%val11 = fmul fast float %arg3, 1.000000e+00
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%val12 = fadd fast float %arg3, 1.000000e+00
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%val13 = fadd fast float %val12, 2.000000e+00
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%val14 = fadd fast float 0.000000e+00, 0.000000e+00
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%val15 = fadd fast float %val14, 1.000000e+00
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%val16 = fadd fast float %arg3, 1.000000e+00
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%val17 = fadd fast float %arg3, 1.000000e+00
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br i1 %arg6, label %bb18, label %bb57
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bb18: ; preds = %bb
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%val19 = phi float [ %val13, %bb ]
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%val20 = phi float [ %val15, %bb ]
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%val21 = phi float [ %val16, %bb ]
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%val22 = phi float [ %val17, %bb ]
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%val23 = fmul fast float %val16, 2.000000e+00
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%val24 = fmul fast float %val17, 3.000000e+00
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br i1 %arg7, label %bb25, label %bb57
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bb25: ; preds = %bb18
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%val26 = phi float [ %val19, %bb18 ]
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%val27 = phi float [ %val20, %bb18 ]
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%val28 = phi float [ %val21, %bb18 ]
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%val29 = phi float [ %val22, %bb18 ]
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br label %bb30
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bb30: ; preds = %bb30, %bb25
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%val31 = phi float [ %val55, %bb30 ], [ 0.000000e+00, %bb25 ]
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%val32 = phi float [ %val9, %bb30 ], [ 0.000000e+00, %bb25 ]
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%val33 = load i8, ptr %arg5, align 1
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%val34 = uitofp i8 %val33 to float
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%val35 = getelementptr inbounds i8, ptr %arg5, i64 1
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%val36 = load i8, ptr %val35, align 1
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%val37 = uitofp i8 %val36 to float
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%val38 = getelementptr inbounds i8, ptr %arg5, i64 2
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%val39 = load i8, ptr %val38, align 1
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%val40 = uitofp i8 %val39 to float
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%val41 = getelementptr inbounds i8, ptr %arg5, i64 3
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%val42 = load i8, ptr %val41, align 1
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%val43 = uitofp i8 %val42 to float
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%val44 = fsub fast float %val34, %val
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%val45 = fsub fast float %val37, %val9
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%val46 = fsub fast float %val40, %val10
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%val47 = fsub fast float %val43, %val11
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%val48 = fmul fast float %val44, %val26
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%val49 = fmul fast float %val45, %val27
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%val50 = fadd fast float %val49, %val48
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%val51 = fmul fast float %val46, %val28
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%val52 = fadd fast float %val50, %val51
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%val53 = fmul fast float %val47, %val29
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%val54 = fadd fast float %val52, %val53
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%val55 = tail call fast float @llvm.minnum.f32(float %val31, float %arg1)
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%val56 = tail call fast float @llvm.maxnum.f32(float %arg2, float %val54)
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call void @ham(float %val55, float %val56)
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br i1 %arg8, label %bb30, label %bb57
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bb57: ; preds = %bb30, %bb18, %bb
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ret i64 0
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}
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declare float @llvm.maxnum.f32(float, float)
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declare float @llvm.minnum.f32(float, float)
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declare void @ham(float, float)
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