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6b5bde697bb6f2ec8564c9b35bbf9f2d5b703f13
clang-p2996/llvm/test/Transforms/SLPVectorizer/AArch64/vectorize-free-extracts-inserts.ll
Alexey Bataev 894935cb51 [SLP]Represent SLP graph as a tree 
We can stop using a graph representation of the SLP structure and switch
directly to tree by relying on a single user of each tree node. If the
node has multiple uses, other uses must be represented as a separate
gather/buildvector node, which then will be combined with the existing
vectorized node(s) uoon cost estimation/codegen.
This allow to simplify inner structure and turn in some extra
optimizations, which could not be turned on for the nodes with multi
users (reordering, minbitwidth analysis).

AVX512, -O3+LTO
Metric: size..text
                                                                               results     results0    diff
         test-suite :: MultiSource/Benchmarks/ASCI_Purple/SMG2000/smg2000.test   253453.00   254253.00  0.3%
                    test-suite :: External/SPEC/CFP2006/444.namd/444.namd.test   251411.00   252051.00  0.3%
                      test-suite :: SingleSource/Benchmarks/Misc/oourafft.test    19114.00    19146.00  0.2%
     test-suite :: External/SPEC/CFP2017speed/638.imagick_s/638.imagick_s.test  1399200.00  1399520.00  0.0%
      test-suite :: External/SPEC/CFP2017rate/538.imagick_r/538.imagick_r.test  1399200.00  1399520.00  0.0%
      test-suite :: MicroBenchmarks/LCALS/SubsetALambdaLoops/lcalsALambda.test   304310.00   304326.00  0.0%
            test-suite :: MicroBenchmarks/LCALS/SubsetARawLoops/lcalsARaw.test   304662.00   304678.00  0.0%
      test-suite :: External/SPEC/CFP2017rate/526.blender_r/526.blender_r.test 12566919.00 12567511.00  0.0%
                test-suite :: External/SPEC/CFP2006/453.povray/453.povray.test  1146300.00  1146316.00  0.0%
        test-suite :: External/SPEC/CFP2017rate/511.povray_r/511.povray_r.test  1159864.00  1159880.00  0.0%
             test-suite :: External/SPEC/CINT2017rate/502.gcc_r/502.gcc_r.test  9407880.00  9407864.00 -0.0%
            test-suite :: External/SPEC/CINT2017speed/602.gcc_s/602.gcc_s.test  9407880.00  9407864.00 -0.0%
               test-suite :: MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4.test  1011612.00  1011596.00 -0.0%
test-suite :: MultiSource/Benchmarks/Prolangs-C/TimberWolfMC/timberwolfmc.test   280584.00   280536.00 -0.0%
     test-suite :: MultiSource/Benchmarks/DOE-ProxyApps-C++/miniFE/miniFE.test    93016.00    93000.00 -0.0%

ASCI_Purple/SMG2000 - extra code vectorized, small variations
CFP2006/444.namd - small variations, less shuffles
Benchmarks/Misc/oourafft - small variations
CFP2017rate/538.imagick_r
CFP2017speed/638.imagick_s - small variations, less shuffles
LCALS/SubsetALambdaLoops - less shuffles
LCALS/SubsetARawLoops - less shuffles
CFP2017rate/526.blender_r - small variations, extra vector code
CFP2006/453.povray - small variations
CFP2017rate/511.povray_r - small variations
CINT2017rate/502.gcc_r
CINT2017speed/602.gcc_s - small variations
Benchmarks/tramp3d-v4 - small variations
Prolangs-C/TimberWolfMC - small variations
DOE-ProxyApps-C++/miniFE - extra code vectorized, small variations
DOE-ProxyApps-C++/CLAMR - extra code vectorized, small variations
ASCI_Purple/SMG2000 - no significant changes

RISCV, -O3+LTO
Metric: size..text
                                                                                          results    results0   diff
test-suite :: SingleSource/Regression/C/gcc-c-torture/execute/GCC-C-execute-pr28982b.test    1812.00    1866.00  3.0%
                            test-suite :: MultiSource/Benchmarks/Olden/health/health.test    3946.00    4016.00  1.8%
                     test-suite :: External/SPEC/CINT2017speed/625.x264_s/625.x264_s.test  513180.00  513550.00  0.1%
                      test-suite :: External/SPEC/CINT2017rate/525.x264_r/525.x264_r.test  513180.00  513550.00  0.1%
                        test-suite :: External/SPEC/CINT2017rate/502.gcc_r/502.gcc_r.test 7672198.00 7672202.00  0.0%
                       test-suite :: External/SPEC/CINT2017speed/602.gcc_s/602.gcc_s.test 7672198.00 7672202.00  0.0%
                       test-suite :: External/SPEC/CFP2017rate/508.namd_r/508.namd_r.test  746060.00  746044.00 -0.0%
                 test-suite :: External/SPEC/CFP2017rate/526.blender_r/526.blender_r.test 9497716.00 9497364.00 -0.0%
                           test-suite :: External/SPEC/CFP2006/453.povray/453.povray.test  948266.00  948214.00 -0.0%
                               test-suite :: External/SPEC/CFP2006/433.milc/433.milc.test   89874.00   89862.00 -0.0%
                            test-suite :: MultiSource/Benchmarks/7zip/7zip-benchmark.test  835492.00  835346.00 -0.0%
                test-suite :: MultiSource/Benchmarks/DOE-ProxyApps-C++/miniFE/miniFE.test   66230.00   66202.00 -0.0%
                   test-suite :: External/SPEC/CFP2017rate/511.povray_r/511.povray_r.test  946090.00  944206.00 -0.2%
                test-suite :: External/SPEC/CFP2017speed/638.imagick_s/638.imagick_s.test 1136404.00 1131854.00 -0.4%
                 test-suite :: External/SPEC/CFP2017rate/538.imagick_r/538.imagick_r.test 1136404.00 1131854.00 -0.4%

gcc-c-torture/execute/GCC-C-execute-pr28982b - better vector code
Olden/health - extra vector code
CINT2017speed/625.x264_s
CINT2017rate/525.x264_r - small variation + improvements in reordering, @pixel_hadamard_ac stopped
being vectorized because of some non-effective shuffle recognition by
the compiler
CINT2017rate/502.gcc_r
CINT2017speed/602.gcc_s - small variations
CFP2017rate/508.namd_r - small variations
CFP2017rate/526.blender_r - small variations
CFP2006/453.povray - extra vector code
Benchmarks/7zip - extra vector code
DOE-ProxyApps-C++/miniFE - small variations
CFP2017rate/511.povray_r - extra vector code
CFP2017speed/638.imagick_s
CFP2017rate/538.imagick_r - extra vector code

Reviewers: RKSimon, hiraditya

Reviewed By: RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/126771
2025-02-21 07:15:02 -05:00

574 lines
32 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes=slp-vectorizer -S %s | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-darwin"
declare void @use(double)
; The extracts %v1.lane.0 and %v1.lane.1 should be considered free during SLP,
; because they will be directly in a vector register on AArch64.
define void @noop_extracts_first_2_lanes(ptr %ptr.1, ptr %ptr.2) {
; CHECK-LABEL: @noop_extracts_first_2_lanes(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[V_1:%.*]] = load <2 x double>, ptr [[PTR_1:%.*]], align 8
; CHECK-NEXT: [[V1_LANE_0:%.*]] = extractelement <2 x double> [[V_1]], i32 0
; CHECK-NEXT: [[V1_LANE_1:%.*]] = extractelement <2 x double> [[V_1]], i32 1
; CHECK-NEXT: [[V_2:%.*]] = load <4 x double>, ptr [[PTR_2:%.*]], align 16
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: [[TMP1:%.*]] = fmul <2 x double> [[V_1]], [[TMP0]]
; CHECK-NEXT: call void @use(double [[V1_LANE_0]])
; CHECK-NEXT: call void @use(double [[V1_LANE_1]])
; CHECK-NEXT: store <2 x double> [[TMP1]], ptr [[PTR_1]], align 8
; CHECK-NEXT: ret void
;
bb:
%v.1 = load <2 x double>, ptr %ptr.1, align 8
%v1.lane.0 = extractelement <2 x double> %v.1, i32 0
%v1.lane.1 = extractelement <2 x double> %v.1, i32 1
%v.2 = load <4 x double>, ptr %ptr.2, align 16
%v2.lane.2 = extractelement <4 x double> %v.2, i32 2
%v2.lane.3 = extractelement <4 x double> %v.2, i32 3
%a.lane.0 = fmul double %v1.lane.0, %v2.lane.2
%a.lane.1 = fmul double %v1.lane.1, %v2.lane.3
%a.ins.0 = insertelement <2 x double> zeroinitializer, double %a.lane.0, i32 0
%a.ins.1 = insertelement <2 x double> %a.ins.0, double %a.lane.1, i32 1
call void @use(double %v1.lane.0)
call void @use(double %v1.lane.1)
store <2 x double> %a.ins.1, ptr %ptr.1, align 8
ret void
}
; Extracts of consecutive indices, but different vector operand.
define void @extracts_first_2_lanes_different_vectors(ptr %ptr.1, ptr %ptr.2, ptr %ptr.3) {
; CHECK-LABEL: @extracts_first_2_lanes_different_vectors(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[V_1:%.*]] = load <2 x double>, ptr [[PTR_1:%.*]], align 8
; CHECK-NEXT: [[V1_LANE_0:%.*]] = extractelement <2 x double> [[V_1]], i32 0
; CHECK-NEXT: [[V_3:%.*]] = load <2 x double>, ptr [[PTR_3:%.*]], align 8
; CHECK-NEXT: [[V3_LANE_1:%.*]] = extractelement <2 x double> [[V_3]], i32 1
; CHECK-NEXT: [[V_2:%.*]] = load <4 x double>, ptr [[PTR_2:%.*]], align 16
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <2 x double> [[V_1]], <2 x double> [[V_3]], <2 x i32> <i32 0, i32 3>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <2 x i32> <i32 2, i32 2>
; CHECK-NEXT: [[TMP2:%.*]] = fmul <2 x double> [[TMP0]], [[TMP1]]
; CHECK-NEXT: call void @use(double [[V1_LANE_0]])
; CHECK-NEXT: call void @use(double [[V3_LANE_1]])
; CHECK-NEXT: store <2 x double> [[TMP2]], ptr [[PTR_1]], align 8
; CHECK-NEXT: ret void
;
bb:
%v.1 = load <2 x double>, ptr %ptr.1, align 8
%v1.lane.0 = extractelement <2 x double> %v.1, i32 0
%v.3 = load <2 x double>, ptr %ptr.3, align 8
%v3.lane.1 = extractelement <2 x double> %v.3, i32 1
%v.2 = load <4 x double>, ptr %ptr.2, align 16
%v2.lane.2 = extractelement <4 x double> %v.2, i32 2
%a.lane.0 = fmul double %v1.lane.0, %v2.lane.2
%a.lane.1 = fmul double %v3.lane.1, %v2.lane.2
%a.ins.0 = insertelement <2 x double> zeroinitializer, double %a.lane.0, i32 0
%a.ins.1 = insertelement <2 x double> %a.ins.0, double %a.lane.1, i32 1
call void @use(double %v1.lane.0)
call void @use(double %v3.lane.1)
store <2 x double> %a.ins.1, ptr %ptr.1, align 8
ret void
}
; The extracts %v1.lane.2 and %v1.lane.3 should be considered free during SLP,
; because they will be directly in a vector register on AArch64.
define void @noop_extract_second_2_lanes(ptr %ptr.1, ptr %ptr.2) {
; CHECK-LABEL: @noop_extract_second_2_lanes(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[V_1:%.*]] = load <4 x double>, ptr [[PTR_1:%.*]], align 8
; CHECK-NEXT: [[V1_LANE_2:%.*]] = extractelement <4 x double> [[V_1]], i32 2
; CHECK-NEXT: [[V1_LANE_3:%.*]] = extractelement <4 x double> [[V_1]], i32 3
; CHECK-NEXT: [[V_2:%.*]] = load <4 x double>, ptr [[PTR_2:%.*]], align 16
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x double> [[V_1]], <4 x double> poison, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <2 x i32> <i32 2, i32 2>
; CHECK-NEXT: [[TMP2:%.*]] = fmul <2 x double> [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x double> zeroinitializer, <4 x double> [[TMP4]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT: call void @use(double [[V1_LANE_2]])
; CHECK-NEXT: call void @use(double [[V1_LANE_3]])
; CHECK-NEXT: store <4 x double> [[TMP3]], ptr [[PTR_1]], align 8
; CHECK-NEXT: ret void
;
bb:
%v.1 = load <4 x double>, ptr %ptr.1, align 8
%v1.lane.2 = extractelement <4 x double> %v.1, i32 2
%v1.lane.3 = extractelement <4 x double> %v.1, i32 3
%v.2 = load <4 x double>, ptr %ptr.2, align 16
%v2.lane.2 = extractelement <4 x double> %v.2, i32 2
%a.lane.0 = fmul double %v1.lane.2, %v2.lane.2
%a.lane.1 = fmul double %v1.lane.3, %v2.lane.2
%a.ins.0 = insertelement <4 x double> zeroinitializer, double %a.lane.0, i32 0
%a.ins.1 = insertelement <4 x double> %a.ins.0, double %a.lane.1, i32 1
call void @use(double %v1.lane.2)
call void @use(double %v1.lane.3)
store <4 x double> %a.ins.1, ptr %ptr.1, align 8
ret void
}
; %v1.lane.0 and %v1.lane.1 are used in reverse-order, so they won't be
; directly in a vector register on AArch64.
define void @extract_reverse_order(ptr %ptr.1, ptr %ptr.2) {
; CHECK-LABEL: @extract_reverse_order(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[V_1:%.*]] = load <2 x double>, ptr [[PTR_1:%.*]], align 8
; CHECK-NEXT: [[V1_LANE_0:%.*]] = extractelement <2 x double> [[V_1]], i32 0
; CHECK-NEXT: [[V1_LANE_1:%.*]] = extractelement <2 x double> [[V_1]], i32 1
; CHECK-NEXT: [[V_2:%.*]] = load <4 x double>, ptr [[PTR_2:%.*]], align 16
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <2 x i32> <i32 2, i32 2>
; CHECK-NEXT: [[TMP1:%.*]] = fmul <2 x double> [[V_1]], [[TMP0]]
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: call void @use(double [[V1_LANE_0]])
; CHECK-NEXT: call void @use(double [[V1_LANE_1]])
; CHECK-NEXT: store <2 x double> [[TMP2]], ptr [[PTR_1]], align 8
; CHECK-NEXT: ret void
;
bb:
%v.1 = load <2 x double>, ptr %ptr.1, align 8
%v1.lane.0 = extractelement <2 x double> %v.1, i32 0
%v1.lane.1 = extractelement <2 x double> %v.1, i32 1
%v.2 = load <4 x double>, ptr %ptr.2, align 16
%v2.lane.2 = extractelement <4 x double> %v.2, i32 2
%a.lane.0 = fmul double %v1.lane.1, %v2.lane.2
%a.lane.1 = fmul double %v1.lane.0, %v2.lane.2
%a.ins.0 = insertelement <2 x double> zeroinitializer, double %a.lane.0, i32 0
%a.ins.1 = insertelement <2 x double> %a.ins.0, double %a.lane.1, i32 1
call void @use(double %v1.lane.0)
call void @use(double %v1.lane.1)
store <2 x double> %a.ins.1, ptr %ptr.1, align 8
ret void
}
; %v1.lane.1 and %v1.lane.2 are extracted from different vector registers on AArch64.
define void @extract_lanes_1_and_2(ptr %ptr.1, ptr %ptr.2) {
; CHECK-LABEL: @extract_lanes_1_and_2(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[V_1:%.*]] = load <4 x double>, ptr [[PTR_1:%.*]], align 8
; CHECK-NEXT: [[V1_LANE_1:%.*]] = extractelement <4 x double> [[V_1]], i32 1
; CHECK-NEXT: [[V1_LANE_2:%.*]] = extractelement <4 x double> [[V_1]], i32 2
; CHECK-NEXT: [[V_2:%.*]] = load <4 x double>, ptr [[PTR_2:%.*]], align 16
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x double> [[V_1]], <4 x double> poison, <2 x i32> <i32 1, i32 2>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <2 x i32> <i32 2, i32 2>
; CHECK-NEXT: [[TMP2:%.*]] = fmul <2 x double> [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x double> zeroinitializer, <4 x double> [[TMP4]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT: call void @use(double [[V1_LANE_1]])
; CHECK-NEXT: call void @use(double [[V1_LANE_2]])
; CHECK-NEXT: store <4 x double> [[TMP3]], ptr [[PTR_1]], align 8
; CHECK-NEXT: ret void
;
bb:
%v.1 = load <4 x double>, ptr %ptr.1, align 8
%v1.lane.1 = extractelement <4 x double> %v.1, i32 1
%v1.lane.2 = extractelement <4 x double> %v.1, i32 2
%v.2 = load <4 x double>, ptr %ptr.2, align 16
%v2.lane.2 = extractelement <4 x double> %v.2, i32 2
%a.lane.0 = fmul double %v1.lane.1, %v2.lane.2
%a.lane.1 = fmul double %v1.lane.2, %v2.lane.2
%a.ins.0 = insertelement <4 x double> zeroinitializer, double %a.lane.0, i32 0
%a.ins.1 = insertelement <4 x double> %a.ins.0, double %a.lane.1, i32 1
call void @use(double %v1.lane.1)
call void @use(double %v1.lane.2)
store <4 x double> %a.ins.1, ptr %ptr.1, align 8
ret void
}
; More complex case where the extracted lanes are directly from a vector
; register on AArch64 and should be considered free, because we can
; directly use the source vector register.
define void @noop_extracts_existing_vector_4_lanes(ptr %ptr.1, ptr %ptr.2) {
; CHECK-LABEL: @noop_extracts_existing_vector_4_lanes(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[V_1:%.*]] = load <9 x double>, ptr [[PTR_1:%.*]], align 8
; CHECK-NEXT: [[V1_LANE_0:%.*]] = extractelement <9 x double> [[V_1]], i32 0
; CHECK-NEXT: [[V1_LANE_1:%.*]] = extractelement <9 x double> [[V_1]], i32 1
; CHECK-NEXT: [[V1_LANE_2:%.*]] = extractelement <9 x double> [[V_1]], i32 2
; CHECK-NEXT: [[V1_LANE_3:%.*]] = extractelement <9 x double> [[V_1]], i32 3
; CHECK-NEXT: [[V_2:%.*]] = load <4 x double>, ptr [[PTR_2:%.*]], align 16
; CHECK-NEXT: [[V2_LANE_1:%.*]] = extractelement <4 x double> [[V_2]], i32 1
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <9 x double> [[V_1]], <9 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <4 x i32> <i32 2, i32 0, i32 2, i32 2>
; CHECK-NEXT: [[TMP2:%.*]] = fmul <4 x double> [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> poison, <9 x i32> <i32 2, i32 3, i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP4]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 4, i32 5, i32 6, i32 7, i32 8>
; CHECK-NEXT: call void @use(double [[V1_LANE_0]])
; CHECK-NEXT: call void @use(double [[V1_LANE_1]])
; CHECK-NEXT: call void @use(double [[V1_LANE_2]])
; CHECK-NEXT: call void @use(double [[V1_LANE_3]])
; CHECK-NEXT: store <9 x double> [[TMP3]], ptr [[PTR_1]], align 8
; CHECK-NEXT: ret void
;
bb:
%v.1 = load <9 x double>, ptr %ptr.1, align 8
%v1.lane.0 = extractelement <9 x double> %v.1, i32 0
%v1.lane.1 = extractelement <9 x double> %v.1, i32 1
%v1.lane.2 = extractelement <9 x double> %v.1, i32 2
%v1.lane.3 = extractelement <9 x double> %v.1, i32 3
%v.2 = load <4 x double>, ptr %ptr.2, align 16
%v2.lane.0 = extractelement <4 x double> %v.2, i32 0
%v2.lane.1 = extractelement <4 x double> %v.2, i32 1
%v2.lane.2 = extractelement <4 x double> %v.2, i32 2
%a.lane.0 = fmul double %v1.lane.2, %v2.lane.2
%a.lane.1 = fmul double %v1.lane.3, %v2.lane.2
%a.lane.2 = fmul double %v1.lane.0, %v2.lane.2
%a.lane.3 = fmul double %v1.lane.1, %v2.lane.0
%a.ins.0 = insertelement <9 x double> zeroinitializer, double %a.lane.0, i32 0
%a.ins.1 = insertelement <9 x double> %a.ins.0, double %a.lane.1, i32 1
%a.ins.2 = insertelement <9 x double> %a.ins.1, double %a.lane.2, i32 2
%a.ins.3 = insertelement <9 x double> %a.ins.2, double %a.lane.3, i32 3
call void @use(double %v1.lane.0)
call void @use(double %v1.lane.1)
call void @use(double %v1.lane.2)
call void @use(double %v1.lane.3)
store <9 x double> %a.ins.3, ptr %ptr.1, align 8
ret void
}
; Extracted lanes are not used in the right order, so we cannot reuse the
; source vector registers directly.
define void @extracts_jumbled_4_lanes(ptr %ptr.1, ptr %ptr.2) {
; CHECK-LABEL: @extracts_jumbled_4_lanes(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[V_1:%.*]] = load <9 x double>, ptr [[PTR_1:%.*]], align 8
; CHECK-NEXT: [[V1_LANE_0:%.*]] = extractelement <9 x double> [[V_1]], i32 0
; CHECK-NEXT: [[V1_LANE_1:%.*]] = extractelement <9 x double> [[V_1]], i32 1
; CHECK-NEXT: [[V1_LANE_2:%.*]] = extractelement <9 x double> [[V_1]], i32 2
; CHECK-NEXT: [[V1_LANE_3:%.*]] = extractelement <9 x double> [[V_1]], i32 3
; CHECK-NEXT: [[V_2:%.*]] = load <4 x double>, ptr [[PTR_2:%.*]], align 16
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <9 x double> [[V_1]], <9 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <4 x i32> <i32 2, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[TMP2:%.*]] = fmul <4 x double> [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> poison, <9 x i32> <i32 0, i32 2, i32 1, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP4]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 4, i32 5, i32 6, i32 7, i32 8>
; CHECK-NEXT: call void @use(double [[V1_LANE_0]])
; CHECK-NEXT: call void @use(double [[V1_LANE_1]])
; CHECK-NEXT: call void @use(double [[V1_LANE_2]])
; CHECK-NEXT: call void @use(double [[V1_LANE_3]])
; CHECK-NEXT: store <9 x double> [[TMP3]], ptr [[PTR_1]], align 8
; CHECK-NEXT: ret void
;
bb:
%v.1 = load <9 x double>, ptr %ptr.1, align 8
%v1.lane.0 = extractelement <9 x double> %v.1, i32 0
%v1.lane.1 = extractelement <9 x double> %v.1, i32 1
%v1.lane.2 = extractelement <9 x double> %v.1, i32 2
%v1.lane.3 = extractelement <9 x double> %v.1, i32 3
%v.2 = load <4 x double>, ptr %ptr.2, align 16
%v2.lane.0 = extractelement <4 x double> %v.2, i32 0
%v2.lane.1 = extractelement <4 x double> %v.2, i32 1
%v2.lane.2 = extractelement <4 x double> %v.2, i32 2
%a.lane.0 = fmul double %v1.lane.0, %v2.lane.2
%a.lane.1 = fmul double %v1.lane.2, %v2.lane.1
%a.lane.2 = fmul double %v1.lane.1, %v2.lane.2
%a.lane.3 = fmul double %v1.lane.3, %v2.lane.0
%a.ins.0 = insertelement <9 x double> zeroinitializer, double %a.lane.0, i32 0
%a.ins.1 = insertelement <9 x double> %a.ins.0, double %a.lane.1, i32 1
%a.ins.2 = insertelement <9 x double> %a.ins.1, double %a.lane.2, i32 2
%a.ins.3 = insertelement <9 x double> %a.ins.2, double %a.lane.3, i32 3
call void @use(double %v1.lane.0)
call void @use(double %v1.lane.1)
call void @use(double %v1.lane.2)
call void @use(double %v1.lane.3)
store <9 x double> %a.ins.3, ptr %ptr.1, align 8
ret void
}
; Even more complex case where the extracted lanes are directly from a vector
; register on AArch64 and should be considered free, because we can
; directly use the source vector register.
define void @noop_extracts_9_lanes(ptr %ptr.1, ptr %ptr.2) {
; CHECK-LABEL: @noop_extracts_9_lanes(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[V_1:%.*]] = load <9 x double>, ptr [[PTR_1:%.*]], align 8
; CHECK-NEXT: [[V1_LANE_2:%.*]] = extractelement <9 x double> [[V_1]], i32 2
; CHECK-NEXT: [[V1_LANE_5:%.*]] = extractelement <9 x double> [[V_1]], i32 5
; CHECK-NEXT: [[V_2:%.*]] = load <4 x double>, ptr [[PTR_2:%.*]], align 16
; CHECK-NEXT: [[V2_LANE_0:%.*]] = extractelement <4 x double> [[V_2]], i32 0
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <9 x double> [[V_1]], <9 x double> poison, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 0, i32 1>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <8 x i32> <i32 0, i32 2, i32 1, i32 0, i32 2, i32 0, i32 2, i32 1>
; CHECK-NEXT: [[TMP2:%.*]] = fmul <8 x double> [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[A_LANE_8:%.*]] = fmul double [[V1_LANE_2]], [[V2_LANE_0]]
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x double> [[TMP2]], <8 x double> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
; CHECK-NEXT: [[A_INS_72:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP3]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
; CHECK-NEXT: [[A_INS_8:%.*]] = insertelement <9 x double> [[A_INS_72]], double [[A_LANE_8]], i32 8
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <9 x double> [[V_1]], <9 x double> poison, <8 x i32> <i32 6, i32 7, i32 8, i32 0, i32 1, i32 2, i32 3, i32 4>
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <8 x i32> <i32 2, i32 1, i32 0, i32 2, i32 1, i32 0, i32 2, i32 1>
; CHECK-NEXT: [[TMP6:%.*]] = fmul <8 x double> [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[B_LANE_8:%.*]] = fmul double [[V1_LANE_5]], [[V2_LANE_0]]
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x double> [[TMP6]], <8 x double> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
; CHECK-NEXT: [[B_INS_71:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP7]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
; CHECK-NEXT: [[B_INS_8:%.*]] = insertelement <9 x double> [[B_INS_71]], double [[B_LANE_8]], i32 8
; CHECK-NEXT: [[RES:%.*]] = fsub <9 x double> [[A_INS_8]], [[B_INS_8]]
; CHECK-NEXT: store <9 x double> [[RES]], ptr [[PTR_1]], align 8
; CHECK-NEXT: ret void
;
bb:
%v.1 = load <9 x double>, ptr %ptr.1, align 8
%v1.lane.0 = extractelement <9 x double> %v.1, i32 0
%v1.lane.1 = extractelement <9 x double> %v.1, i32 1
%v1.lane.2 = extractelement <9 x double> %v.1, i32 2
%v1.lane.3 = extractelement <9 x double> %v.1, i32 3
%v1.lane.4 = extractelement <9 x double> %v.1, i32 4
%v1.lane.5 = extractelement <9 x double> %v.1, i32 5
%v1.lane.6 = extractelement <9 x double> %v.1, i32 6
%v1.lane.7 = extractelement <9 x double> %v.1, i32 7
%v1.lane.8 = extractelement <9 x double> %v.1, i32 8
%v.2 = load <4 x double>, ptr %ptr.2, align 16
%v2.lane.0 = extractelement <4 x double> %v.2, i32 0
%v2.lane.1 = extractelement <4 x double> %v.2, i32 1
%v2.lane.2 = extractelement <4 x double> %v.2, i32 2
%a.lane.0 = fmul double %v1.lane.3, %v2.lane.0
%a.lane.1 = fmul double %v1.lane.4, %v2.lane.2
%a.lane.2 = fmul double %v1.lane.5, %v2.lane.1
%a.lane.3 = fmul double %v1.lane.6, %v2.lane.0
%a.lane.4 = fmul double %v1.lane.7, %v2.lane.2
%a.lane.5 = fmul double %v1.lane.8, %v2.lane.0
%a.lane.6 = fmul double %v1.lane.0, %v2.lane.2
%a.lane.7 = fmul double %v1.lane.1, %v2.lane.1
%a.lane.8 = fmul double %v1.lane.2, %v2.lane.0
%a.ins.0 = insertelement <9 x double> zeroinitializer, double %a.lane.0, i32 0
%a.ins.1 = insertelement <9 x double> %a.ins.0, double %a.lane.1, i32 1
%a.ins.2 = insertelement <9 x double> %a.ins.1, double %a.lane.2, i32 2
%a.ins.3 = insertelement <9 x double> %a.ins.2, double %a.lane.3, i32 3
%a.ins.4 = insertelement <9 x double> %a.ins.3, double %a.lane.4, i32 4
%a.ins.5 = insertelement <9 x double> %a.ins.4, double %a.lane.5, i32 5
%a.ins.6 = insertelement <9 x double> %a.ins.5, double %a.lane.6, i32 6
%a.ins.7 = insertelement <9 x double> %a.ins.6, double %a.lane.7, i32 7
%a.ins.8 = insertelement <9 x double> %a.ins.7, double %a.lane.8, i32 8
%b.lane.0 = fmul double %v1.lane.6, %v2.lane.2
%b.lane.1 = fmul double %v1.lane.7, %v2.lane.1
%b.lane.2 = fmul double %v1.lane.8, %v2.lane.0
%b.lane.3 = fmul double %v1.lane.0, %v2.lane.2
%b.lane.4 = fmul double %v1.lane.1, %v2.lane.1
%b.lane.5 = fmul double %v1.lane.2, %v2.lane.0
%b.lane.6 = fmul double %v1.lane.3, %v2.lane.2
%b.lane.7 = fmul double %v1.lane.4, %v2.lane.1
%b.lane.8 = fmul double %v1.lane.5, %v2.lane.0
%b.ins.0 = insertelement <9 x double> zeroinitializer, double %b.lane.0, i32 0
%b.ins.1 = insertelement <9 x double> %b.ins.0, double %b.lane.1, i32 1
%b.ins.2 = insertelement <9 x double> %b.ins.1, double %b.lane.2, i32 2
%b.ins.3 = insertelement <9 x double> %b.ins.2, double %b.lane.3, i32 3
%b.ins.4 = insertelement <9 x double> %b.ins.3, double %b.lane.4, i32 4
%b.ins.5 = insertelement <9 x double> %b.ins.4, double %b.lane.5, i32 5
%b.ins.6 = insertelement <9 x double> %b.ins.5, double %b.lane.6, i32 6
%b.ins.7 = insertelement <9 x double> %b.ins.6, double %b.lane.7, i32 7
%b.ins.8 = insertelement <9 x double> %b.ins.7, double %b.lane.8, i32 8
%res = fsub <9 x double> %a.ins.8, %b.ins.8
store <9 x double> %res, ptr %ptr.1, align 8
ret void
}
; Extracted lanes used in first fmul chain are not used in the right order, so
; we cannot reuse the source vector registers directly.
define void @first_mul_chain_jumbled(ptr %ptr.1, ptr %ptr.2) {
; CHECK-LABEL: @first_mul_chain_jumbled(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[V_1:%.*]] = load <9 x double>, ptr [[PTR_1:%.*]], align 8
; CHECK-NEXT: [[V1_LANE_2:%.*]] = extractelement <9 x double> [[V_1]], i32 2
; CHECK-NEXT: [[V1_LANE_5:%.*]] = extractelement <9 x double> [[V_1]], i32 5
; CHECK-NEXT: [[V_2:%.*]] = load <4 x double>, ptr [[PTR_2:%.*]], align 16
; CHECK-NEXT: [[V2_LANE_0:%.*]] = extractelement <4 x double> [[V_2]], i32 0
; CHECK-NEXT: [[V2_LANE_1:%.*]] = extractelement <4 x double> [[V_2]], i32 1
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <9 x double> [[V_1]], <9 x double> poison, <8 x i32> <i32 4, i32 3, i32 6, i32 5, i32 8, i32 7, i32 1, i32 0>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <8 x i32> <i32 1, i32 0, i32 2, i32 0, i32 2, i32 1, i32 0, i32 2>
; CHECK-NEXT: [[TMP2:%.*]] = fmul <8 x double> [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[A_LANE_8:%.*]] = fmul double [[V1_LANE_2]], [[V2_LANE_1]]
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x double> [[TMP2]], <8 x double> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
; CHECK-NEXT: [[A_INS_72:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP3]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
; CHECK-NEXT: [[A_INS_8:%.*]] = insertelement <9 x double> [[A_INS_72]], double [[A_LANE_8]], i32 8
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <9 x double> [[V_1]], <9 x double> poison, <8 x i32> <i32 6, i32 7, i32 8, i32 0, i32 1, i32 2, i32 3, i32 4>
; CHECK-NEXT: [[TMP5:%.*]] = fmul <8 x double> [[TMP4]], [[TMP1]]
; CHECK-NEXT: [[B_LANE_8:%.*]] = fmul double [[V1_LANE_5]], [[V2_LANE_0]]
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <8 x double> [[TMP5]], <8 x double> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
; CHECK-NEXT: [[B_INS_71:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP6]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
; CHECK-NEXT: [[B_INS_8:%.*]] = insertelement <9 x double> [[B_INS_71]], double [[B_LANE_8]], i32 8
; CHECK-NEXT: [[RES:%.*]] = fsub <9 x double> [[A_INS_8]], [[B_INS_8]]
; CHECK-NEXT: store <9 x double> [[RES]], ptr [[PTR_1]], align 8
; CHECK-NEXT: ret void
;
bb:
%v.1 = load <9 x double>, ptr %ptr.1, align 8
%v1.lane.0 = extractelement <9 x double> %v.1, i32 0
%v1.lane.1 = extractelement <9 x double> %v.1, i32 1
%v1.lane.2 = extractelement <9 x double> %v.1, i32 2
%v1.lane.3 = extractelement <9 x double> %v.1, i32 3
%v1.lane.4 = extractelement <9 x double> %v.1, i32 4
%v1.lane.5 = extractelement <9 x double> %v.1, i32 5
%v1.lane.6 = extractelement <9 x double> %v.1, i32 6
%v1.lane.7 = extractelement <9 x double> %v.1, i32 7
%v1.lane.8 = extractelement <9 x double> %v.1, i32 8
%v.2 = load <4 x double>, ptr %ptr.2, align 16
%v2.lane.0 = extractelement <4 x double> %v.2, i32 0
%v2.lane.1 = extractelement <4 x double> %v.2, i32 1
%v2.lane.2 = extractelement <4 x double> %v.2, i32 2
%a.lane.0 = fmul double %v1.lane.4, %v2.lane.1
%a.lane.1 = fmul double %v1.lane.3, %v2.lane.0
%a.lane.2 = fmul double %v1.lane.6, %v2.lane.2
%a.lane.3 = fmul double %v1.lane.5, %v2.lane.0
%a.lane.4 = fmul double %v1.lane.8, %v2.lane.2
%a.lane.5 = fmul double %v1.lane.7, %v2.lane.1
%a.lane.6 = fmul double %v1.lane.1, %v2.lane.0
%a.lane.7 = fmul double %v1.lane.0, %v2.lane.2
%a.lane.8 = fmul double %v1.lane.2, %v2.lane.1
%a.ins.0 = insertelement <9 x double> zeroinitializer, double %a.lane.0, i32 0
%a.ins.1 = insertelement <9 x double> %a.ins.0, double %a.lane.1, i32 1
%a.ins.2 = insertelement <9 x double> %a.ins.1, double %a.lane.2, i32 2
%a.ins.3 = insertelement <9 x double> %a.ins.2, double %a.lane.3, i32 3
%a.ins.4 = insertelement <9 x double> %a.ins.3, double %a.lane.4, i32 4
%a.ins.5 = insertelement <9 x double> %a.ins.4, double %a.lane.5, i32 5
%a.ins.6 = insertelement <9 x double> %a.ins.5, double %a.lane.6, i32 6
%a.ins.7 = insertelement <9 x double> %a.ins.6, double %a.lane.7, i32 7
%a.ins.8 = insertelement <9 x double> %a.ins.7, double %a.lane.8, i32 8
%b.lane.0 = fmul double %v1.lane.6, %v2.lane.1
%b.lane.1 = fmul double %v1.lane.7, %v2.lane.0
%b.lane.2 = fmul double %v1.lane.8, %v2.lane.2
%b.lane.3 = fmul double %v1.lane.0, %v2.lane.0
%b.lane.4 = fmul double %v1.lane.1, %v2.lane.2
%b.lane.5 = fmul double %v1.lane.2, %v2.lane.1
%b.lane.6 = fmul double %v1.lane.3, %v2.lane.0
%b.lane.7 = fmul double %v1.lane.4, %v2.lane.2
%b.lane.8 = fmul double %v1.lane.5, %v2.lane.0
%b.ins.0 = insertelement <9 x double> zeroinitializer, double %b.lane.0, i32 0
%b.ins.1 = insertelement <9 x double> %b.ins.0, double %b.lane.1, i32 1
%b.ins.2 = insertelement <9 x double> %b.ins.1, double %b.lane.2, i32 2
%b.ins.3 = insertelement <9 x double> %b.ins.2, double %b.lane.3, i32 3
%b.ins.4 = insertelement <9 x double> %b.ins.3, double %b.lane.4, i32 4
%b.ins.5 = insertelement <9 x double> %b.ins.4, double %b.lane.5, i32 5
%b.ins.6 = insertelement <9 x double> %b.ins.5, double %b.lane.6, i32 6
%b.ins.7 = insertelement <9 x double> %b.ins.6, double %b.lane.7, i32 7
%b.ins.8 = insertelement <9 x double> %b.ins.7, double %b.lane.8, i32 8
%res = fsub <9 x double> %a.ins.8, %b.ins.8
store <9 x double> %res, ptr %ptr.1, align 8
ret void
}
; Extracted lanes used in both fmul chain are not used in the right order, so
; we cannot reuse the source vector registers directly.
define void @first_and_second_mul_chain_jumbled(ptr %ptr.1, ptr %ptr.2) {
; CHECK-LABEL: @first_and_second_mul_chain_jumbled(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[V_1:%.*]] = load <9 x double>, ptr [[PTR_1:%.*]], align 8
; CHECK-NEXT: [[V1_LANE_2:%.*]] = extractelement <9 x double> [[V_1]], i32 2
; CHECK-NEXT: [[V1_LANE_4:%.*]] = extractelement <9 x double> [[V_1]], i32 4
; CHECK-NEXT: [[V_2:%.*]] = load <4 x double>, ptr [[PTR_2:%.*]], align 16
; CHECK-NEXT: [[V2_LANE_0:%.*]] = extractelement <4 x double> [[V_2]], i32 0
; CHECK-NEXT: [[V2_LANE_2:%.*]] = extractelement <4 x double> [[V_2]], i32 2
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <9 x double> [[V_1]], <9 x double> poison, <8 x i32> <i32 4, i32 3, i32 5, i32 6, i32 8, i32 7, i32 1, i32 0>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <8 x i32> <i32 0, i32 2, i32 1, i32 2, i32 1, i32 0, i32 2, i32 1>
; CHECK-NEXT: [[TMP2:%.*]] = fmul <8 x double> [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[A_LANE_8:%.*]] = fmul double [[V1_LANE_2]], [[V2_LANE_0]]
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x double> [[TMP2]], <8 x double> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
; CHECK-NEXT: [[A_INS_72:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP3]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
; CHECK-NEXT: [[A_INS_8:%.*]] = insertelement <9 x double> [[A_INS_72]], double [[A_LANE_8]], i32 8
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <9 x double> [[V_1]], <9 x double> poison, <8 x i32> <i32 7, i32 6, i32 8, i32 1, i32 0, i32 3, i32 2, i32 5>
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <8 x i32> <i32 2, i32 1, i32 0, i32 2, i32 0, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[TMP6:%.*]] = fmul <8 x double> [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[B_LANE_8:%.*]] = fmul double [[V1_LANE_4]], [[V2_LANE_2]]
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x double> [[TMP6]], <8 x double> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
; CHECK-NEXT: [[B_INS_71:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP7]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
; CHECK-NEXT: [[B_INS_8:%.*]] = insertelement <9 x double> [[B_INS_71]], double [[B_LANE_8]], i32 8
; CHECK-NEXT: [[RES:%.*]] = fsub <9 x double> [[A_INS_8]], [[B_INS_8]]
; CHECK-NEXT: store <9 x double> [[RES]], ptr [[PTR_1]], align 8
; CHECK-NEXT: ret void
;
bb:
%v.1 = load <9 x double>, ptr %ptr.1, align 8
%v1.lane.0 = extractelement <9 x double> %v.1, i32 0
%v1.lane.1 = extractelement <9 x double> %v.1, i32 1
%v1.lane.2 = extractelement <9 x double> %v.1, i32 2
%v1.lane.3 = extractelement <9 x double> %v.1, i32 3
%v1.lane.4 = extractelement <9 x double> %v.1, i32 4
%v1.lane.5 = extractelement <9 x double> %v.1, i32 5
%v1.lane.6 = extractelement <9 x double> %v.1, i32 6
%v1.lane.7 = extractelement <9 x double> %v.1, i32 7
%v1.lane.8 = extractelement <9 x double> %v.1, i32 8
%v.2 = load <4 x double>, ptr %ptr.2, align 16
%v2.lane.0 = extractelement <4 x double> %v.2, i32 0
%v2.lane.1 = extractelement <4 x double> %v.2, i32 1
%v2.lane.2 = extractelement <4 x double> %v.2, i32 2
%a.lane.0 = fmul double %v1.lane.4, %v2.lane.0
%a.lane.1 = fmul double %v1.lane.3, %v2.lane.2
%a.lane.2 = fmul double %v1.lane.5, %v2.lane.1
%a.lane.3 = fmul double %v1.lane.6, %v2.lane.2
%a.lane.4 = fmul double %v1.lane.8, %v2.lane.1
%a.lane.5 = fmul double %v1.lane.7, %v2.lane.0
%a.lane.6 = fmul double %v1.lane.1, %v2.lane.2
%a.lane.7 = fmul double %v1.lane.0, %v2.lane.1
%a.lane.8 = fmul double %v1.lane.2, %v2.lane.0
%a.ins.0 = insertelement <9 x double> zeroinitializer, double %a.lane.0, i32 0
%a.ins.1 = insertelement <9 x double> %a.ins.0, double %a.lane.1, i32 1
%a.ins.2 = insertelement <9 x double> %a.ins.1, double %a.lane.2, i32 2
%a.ins.3 = insertelement <9 x double> %a.ins.2, double %a.lane.3, i32 3
%a.ins.4 = insertelement <9 x double> %a.ins.3, double %a.lane.4, i32 4
%a.ins.5 = insertelement <9 x double> %a.ins.4, double %a.lane.5, i32 5
%a.ins.6 = insertelement <9 x double> %a.ins.5, double %a.lane.6, i32 6
%a.ins.7 = insertelement <9 x double> %a.ins.6, double %a.lane.7, i32 7
%a.ins.8 = insertelement <9 x double> %a.ins.7, double %a.lane.8, i32 8
%b.lane.0 = fmul double %v1.lane.7, %v2.lane.2
%b.lane.1 = fmul double %v1.lane.6, %v2.lane.1
%b.lane.2 = fmul double %v1.lane.8, %v2.lane.0
%b.lane.3 = fmul double %v1.lane.1, %v2.lane.2
%b.lane.4 = fmul double %v1.lane.0, %v2.lane.0
%b.lane.5 = fmul double %v1.lane.3, %v2.lane.2
%b.lane.6 = fmul double %v1.lane.2, %v2.lane.1
%b.lane.7 = fmul double %v1.lane.5, %v2.lane.0
%b.lane.8 = fmul double %v1.lane.4, %v2.lane.2
%b.ins.0 = insertelement <9 x double> zeroinitializer, double %b.lane.0, i32 0
%b.ins.1 = insertelement <9 x double> %b.ins.0, double %b.lane.1, i32 1
%b.ins.2 = insertelement <9 x double> %b.ins.1, double %b.lane.2, i32 2
%b.ins.3 = insertelement <9 x double> %b.ins.2, double %b.lane.3, i32 3
%b.ins.4 = insertelement <9 x double> %b.ins.3, double %b.lane.4, i32 4
%b.ins.5 = insertelement <9 x double> %b.ins.4, double %b.lane.5, i32 5
%b.ins.6 = insertelement <9 x double> %b.ins.5, double %b.lane.6, i32 6
%b.ins.7 = insertelement <9 x double> %b.ins.6, double %b.lane.7, i32 7
%b.ins.8 = insertelement <9 x double> %b.ins.7, double %b.lane.8, i32 8
%res = fsub <9 x double> %a.ins.8, %b.ins.8
store <9 x double> %res, ptr %ptr.1, align 8
ret void
}
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