10b99e97ff
Up until now the generation of vector instructions was taking place during the top-down post-order traversal of vectorizeRec(). The issue with this approach is that the vector instructions emitted during the traversal can be reordered by the scheduler, making it challenging to place them without breaking the def-before-uses rule. With this patch we separate the vectorization decisions (done in `vectorizeRec()`) from the code generation phase (`emitVectors()`). The vectorization decisions are stored in the `Actions` vector and are used by `emitVectors()` to drive code generation.
77 lines
3.8 KiB
LLVM
77 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -passes=sandbox-vectorizer -sbvec-vec-reg-bits=1024 -sbvec-allow-non-pow2 -sbvec-passes="seed-collection<tr-save,bottom-up-vec,tr-accept>" %s -S | FileCheck %s
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; This used to crash because the newly added pack instructions would not update
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; the DAG and scheduler, leading to def-after-use.
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define void @check_dag_scheduler_update(ptr noalias %p, ptr noalias %p1) {
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; CHECK-LABEL: define void @check_dag_scheduler_update(
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; CHECK-SAME: ptr noalias [[P:%.*]], ptr noalias [[P1:%.*]]) {
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; CHECK-NEXT: [[I:%.*]] = load i32, ptr [[P]], align 4
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; CHECK-NEXT: [[VECL:%.*]] = load <4 x i32>, ptr [[P]], align 4
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; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr i32, ptr [[P]], i64 34
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; CHECK-NEXT: [[I2:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4
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; CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr i32, ptr [[P]], i64 33
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; CHECK-NEXT: [[I4:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4
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; CHECK-NEXT: [[ARRAYIDX18:%.*]] = getelementptr i32, ptr [[P]], i64 32
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; CHECK-NEXT: [[I6:%.*]] = load i32, ptr [[ARRAYIDX18]], align 4
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; CHECK-NEXT: [[PACK:%.*]] = insertelement <4 x i32> poison, i32 [[I]], i32 0
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; CHECK-NEXT: [[PACK1:%.*]] = insertelement <4 x i32> [[PACK]], i32 [[I6]], i32 1
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; CHECK-NEXT: [[PACK2:%.*]] = insertelement <4 x i32> [[PACK1]], i32 [[I4]], i32 2
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; CHECK-NEXT: [[PACK3:%.*]] = insertelement <4 x i32> [[PACK2]], i32 [[I2]], i32 3
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; CHECK-NEXT: [[VEC:%.*]] = add nsw <4 x i32> [[PACK3]], [[VECL]]
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; CHECK-NEXT: store <4 x i32> [[VEC]], ptr [[P1]], align 4
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; CHECK-NEXT: ret void
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;
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%i = load i32, ptr %p
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%i1 = load i32, ptr %p
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%add = add nsw i32 %i, %i1
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store i32 %add, ptr %p1
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%arrayidx4 = getelementptr i32, ptr %p, i64 32
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%i2 = load i32, ptr %arrayidx4
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%arrayidx6 = getelementptr i32, ptr %p, i64 1
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%i3 = load i32, ptr %arrayidx6
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%add7 = add nsw i32 %i2, %i3
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%arrayidx9 = getelementptr i32, ptr %p1, i64 1
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store i32 %add7, ptr %arrayidx9
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%arrayidx11 = getelementptr i32, ptr %p, i64 33
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%i4 = load i32, ptr %arrayidx11
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%arrayidx13 = getelementptr i32, ptr %p, i64 2
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%i5 = load i32, ptr %arrayidx13
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%add14 = add nsw i32 %i4, %i5
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%arrayidx16 = getelementptr i32, ptr %p1, i64 2
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store i32 %add14, ptr %arrayidx16
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%arrayidx18 = getelementptr i32, ptr %p, i64 34
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%i6 = load i32, ptr %arrayidx18
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%arrayidx19 = getelementptr i32, ptr %p, i64 3
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%i7 = load i32, ptr %arrayidx19
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%add21 = add nsw i32 %i6, %i7
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%arrayidx23 = getelementptr i32, ptr %p1, i64 3
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store i32 %add21, ptr %arrayidx23
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ret void
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}
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; This used to generate use-before-def because of a buggy update of the
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; top-of-schedule variable.
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define <4 x float> @check_top_of_schedule(ptr %0) {
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; CHECK-LABEL: define <4 x float> @check_top_of_schedule(
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; CHECK-SAME: ptr [[TMP0:%.*]]) {
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; CHECK-NEXT: [[INS_1:%.*]] = insertelement <4 x float> zeroinitializer, float poison, i64 0
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; CHECK-NEXT: [[TRUNC_1:%.*]] = fptrunc double 0.000000e+00 to float
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; CHECK-NEXT: [[INS_2:%.*]] = insertelement <4 x float> [[INS_1]], float [[TRUNC_1]], i64 0
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; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr double, ptr [[TMP0]], i64 1
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; CHECK-NEXT: store <2 x double> <double 0.000000e+00, double 1.000000e+00>, ptr [[GEP_1]], align 8
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; CHECK-NEXT: ret <4 x float> [[INS_2]]
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;
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%trunc.1 = fptrunc double 0.000000e+00 to float
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%trunc.2 = fptrunc double 1.000000e+00 to float
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%ins.1 = insertelement <4 x float> zeroinitializer, float poison, i64 0
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%ins.2 = insertelement <4 x float> %ins.1, float %trunc.1, i64 0
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%ext.1 = fpext float %trunc.1 to double
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%gep.1 = getelementptr double, ptr %0, i64 1
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store double %ext.1, ptr %gep.1, align 8
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%ext.2 = fpext float %trunc.2 to double
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%gep.2 = getelementptr double, ptr %0, i64 2
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store double %ext.2, ptr %gep.2, align 8
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ret <4 x float> %ins.2
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}
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