67d3ef74b3
This PR continues https://github.com/llvm/llvm-project/pull/101732 changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. Namely, the following changes are introduced: * register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected and simplified (by removing unnecessary sophisticated options) -- e.g., this PR gets rid of duplicating 32/64 bits patterns, removes ANYID register class and simplifies definition of the rest of register classes, * hardcoded LLT scalar types in passes before instruction selection are corrected -- the goal is to have correct bit width before instruction selection, and use 64 bits registers for pattern matching in the instruction selection pass; 32-bit registers remain where they are described in such terms by SPIR-V specification (like, for example, creation of virtual registers for scope/mem semantics operands), * rework virtual register type/class assignment for calls/builtins lowering, * a series of minor changes to fix validity of emitted code between passes: - ensure that that bitcast changes the type, - fix the pattern for instruction selection for OpExtInst, - simplify inline asm operands usage, - account for arbitrary integer sizes / update legalizer rules; * add '-verify-machineinstrs' to existed test cases. See also https://github.com/llvm/llvm-project/issues/88129 that this PR may resolve. This PR fixes a great number of issues reported by MachineVerifier and, as a result, reduces a number of failed test cases for the mode with expensive checks set on from ~200 to ~57.
62 lines
1.9 KiB
LLVM
62 lines
1.9 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
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; CHECK-DAG: OpName %[[#BAR:]] "bar"
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; CHECK-DAG: OpName %[[#FOO:]] "foo"
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; CHECK-DAG: OpName %[[#GOO:]] "goo"
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; CHECK-DAG: %[[#INT:]] = OpTypeInt 32
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; CHECK-DAG: %[[#STACK_PTR_INT:]] = OpTypePointer Function %[[#INT]]
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; CHECK-DAG: %[[#GLOBAL_PTR_INT:]] = OpTypePointer CrossWorkgroup %[[#INT]]
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; CHECK-DAG: %[[#FN1:]] = OpTypeFunction %[[#INT]] %[[#INT]]
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; CHECK-DAG: %[[#FN2:]] = OpTypeFunction %[[#INT]] %[[#INT]] %[[#GLOBAL_PTR_INT]]
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define i32 @bar(i32 %a) {
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%p = alloca i32
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store i32 %a, i32* %p
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%b = load i32, i32* %p
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ret i32 %b
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}
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; CHECK: %[[#BAR]] = OpFunction %[[#INT]] None %[[#FN1]]
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; CHECK: %[[#A:]] = OpFunctionParameter %[[#INT]]
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; CHECK: OpLabel
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; CHECK: %[[#P:]] = OpVariable %[[#STACK_PTR_INT]] Function
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; CHECK: OpStore %[[#P]] %[[#A]]
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; CHECK: %[[#B:]] = OpLoad %[[#INT]] %[[#P]]
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; CHECK: OpReturnValue %[[#B]]
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; CHECK: OpFunctionEnd
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define i32 @foo(i32 %a) {
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%p = alloca i32
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store volatile i32 %a, i32* %p
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%b = load volatile i32, i32* %p
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ret i32 %b
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}
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; CHECK: %[[#FOO]] = OpFunction %[[#INT]] None %[[#FN1]]
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; CHECK: %[[#A:]] = OpFunctionParameter %[[#INT]]
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; CHECK: OpLabel
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; CHECK: %[[#P:]] = OpVariable %[[#STACK_PTR_INT]] Function
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; CHECK: OpStore %[[#P]] %[[#A]] Volatile
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; CHECK: %[[#B:]] = OpLoad %[[#INT]] %[[#P]] Volatile
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; CHECK: OpReturnValue %[[#B]]
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; CHECK: OpFunctionEnd
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;; Test load and store in global address space.
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define i32 @goo(i32 %a, ptr addrspace(1) %p) {
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store i32 %a, i32 addrspace(1)* %p
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%b = load i32, i32 addrspace(1)* %p
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ret i32 %b
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}
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; CHECK: %[[#GOO]] = OpFunction %[[#INT]] None %[[#FN2]]
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; CHECK: %[[#A:]] = OpFunctionParameter %[[#INT]]
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; CHECK: %[[#P:]] = OpFunctionParameter %[[#GLOBAL_PTR_INT]]
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; CHECK: OpLabel
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; CHECK: OpStore %[[#P]] %[[#A]]
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; CHECK: %[[#B:]] = OpLoad %[[#INT]] %[[#P]]
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; CHECK: OpReturnValue %[[#B]]
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; CHECK: OpFunctionEnd
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