b1703ad38d
A new test added for spirv-friendly builtins for SPV_KHR_bit_instructions unveiled that current mechanism to detect whether SPIRV Backend is in OpenCL environment or Vulkan environment was not good enough. This PR updates how to detect the environment and all the tests accordingly. *UPDATE*: the new approach is having a new member in `SPIRVSubtarget` to represent the environment. It can be either OpenCL, Kernel or Unknown. If the triple is explicit, we can directly set it at the creation of the `SPIRVSubtarget`, otherwise we just leave it unknown until we find other information that can help us set the environment. For now, the only other information we use to set the environment is `hlsl.shader` attribute at `SPIRV::ExecutionModel::ExecutionModel getExecutionModel(const SPIRVSubtarget &STI, const Function &F)`. Going forward we should consider also specific instructions that are Kernel-exclusive or Shader-exclusive. --------- Co-authored-by: marcos.maronas <mmaronas@smtp.igk.intel.com>
211 lines
6.5 KiB
LLVM
211 lines
6.5 KiB
LLVM
; RUN: llc -O0 -mtriple=spirv-unknown-vulkan %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan %s -o - -filetype=obj | spirv-val %}
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define spir_func noundef i32 @test_branch(i32 noundef %X) {
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entry:
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; CHECK-LABEL: ; -- Begin function test_branch
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; CHECK: OpSelectionMerge %[[#]] DontFlatten
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%X.addr = alloca i32, align 4
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%resp = alloca i32, align 4
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store i32 %X, ptr %X.addr, align 4
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%0 = load i32, ptr %X.addr, align 4
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%cmp = icmp sgt i32 %0, 0
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br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !0
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if.then: ; preds = %entry
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%1 = load i32, ptr %X.addr, align 4
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%sub = sub nsw i32 0, %1
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store i32 %sub, ptr %resp, align 4
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br label %if.end
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if.else: ; preds = %entry
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%2 = load i32, ptr %X.addr, align 4
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%mul = mul nsw i32 %2, 2
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store i32 %mul, ptr %resp, align 4
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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%3 = load i32, ptr %resp, align 4
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ret i32 %3
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}
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define spir_func noundef i32 @test_flatten(i32 noundef %X) {
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entry:
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; CHECK-LABEL: ; -- Begin function test_flatten
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; CHECK: OpSelectionMerge %[[#]] Flatten
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%X.addr = alloca i32, align 4
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%resp = alloca i32, align 4
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store i32 %X, ptr %X.addr, align 4
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%0 = load i32, ptr %X.addr, align 4
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%cmp = icmp sgt i32 %0, 0
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br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !1
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if.then: ; preds = %entry
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%1 = load i32, ptr %X.addr, align 4
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%sub = sub nsw i32 0, %1
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store i32 %sub, ptr %resp, align 4
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br label %if.end
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if.else: ; preds = %entry
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%2 = load i32, ptr %X.addr, align 4
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%mul = mul nsw i32 %2, 2
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store i32 %mul, ptr %resp, align 4
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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%3 = load i32, ptr %resp, align 4
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ret i32 %3
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}
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define spir_func noundef i32 @test_no_attr(i32 noundef %X) {
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entry:
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; CHECK-LABEL: ; -- Begin function test_no_attr
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; CHECK: OpSelectionMerge %[[#]] None
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%X.addr = alloca i32, align 4
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%resp = alloca i32, align 4
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store i32 %X, ptr %X.addr, align 4
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%0 = load i32, ptr %X.addr, align 4
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%cmp = icmp sgt i32 %0, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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%1 = load i32, ptr %X.addr, align 4
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%sub = sub nsw i32 0, %1
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store i32 %sub, ptr %resp, align 4
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br label %if.end
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if.else: ; preds = %entry
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%2 = load i32, ptr %X.addr, align 4
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%mul = mul nsw i32 %2, 2
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store i32 %mul, ptr %resp, align 4
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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%3 = load i32, ptr %resp, align 4
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ret i32 %3
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}
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define spir_func noundef i32 @flatten_switch(i32 noundef %X) {
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entry:
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; CHECK-LABEL: ; -- Begin function flatten_switch
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; CHECK: OpSelectionMerge %[[#]] Flatten
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%X.addr = alloca i32, align 4
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%resp = alloca i32, align 4
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store i32 %X, ptr %X.addr, align 4
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%0 = load i32, ptr %X.addr, align 4
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switch i32 %0, label %sw.epilog [
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i32 0, label %sw.bb
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i32 1, label %sw.bb1
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i32 2, label %sw.bb2
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], !hlsl.controlflow.hint !1
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sw.bb: ; preds = %entry
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%1 = load i32, ptr %X.addr, align 4
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%sub = sub nsw i32 0, %1
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store i32 %sub, ptr %resp, align 4
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br label %sw.epilog
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sw.bb1: ; preds = %entry
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%2 = load i32, ptr %X.addr, align 4
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%3 = load i32, ptr %X.addr, align 4
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%add = add nsw i32 %2, %3
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store i32 %add, ptr %resp, align 4
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br label %sw.epilog
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sw.bb2: ; preds = %entry
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%4 = load i32, ptr %X.addr, align 4
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%5 = load i32, ptr %X.addr, align 4
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%mul = mul nsw i32 %4, %5
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store i32 %mul, ptr %resp, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %entry, %sw.bb2, %sw.bb1, %sw.bb
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%6 = load i32, ptr %resp, align 4
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ret i32 %6
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}
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define spir_func noundef i32 @branch_switch(i32 noundef %X) {
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entry:
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; CHECK-LABEL: ; -- Begin function branch_switch
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; CHECK: OpSelectionMerge %[[#]] DontFlatten
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%X.addr = alloca i32, align 4
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%resp = alloca i32, align 4
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store i32 %X, ptr %X.addr, align 4
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%0 = load i32, ptr %X.addr, align 4
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switch i32 %0, label %sw.epilog [
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i32 0, label %sw.bb
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i32 1, label %sw.bb1
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i32 2, label %sw.bb2
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], !hlsl.controlflow.hint !0
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sw.bb: ; preds = %entry
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%1 = load i32, ptr %X.addr, align 4
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%sub = sub nsw i32 0, %1
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store i32 %sub, ptr %resp, align 4
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br label %sw.epilog
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sw.bb1: ; preds = %entry
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%2 = load i32, ptr %X.addr, align 4
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%3 = load i32, ptr %X.addr, align 4
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%add = add nsw i32 %2, %3
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store i32 %add, ptr %resp, align 4
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br label %sw.epilog
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sw.bb2: ; preds = %entry
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%4 = load i32, ptr %X.addr, align 4
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%5 = load i32, ptr %X.addr, align 4
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%mul = mul nsw i32 %4, %5
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store i32 %mul, ptr %resp, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %entry, %sw.bb2, %sw.bb1, %sw.bb
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%6 = load i32, ptr %resp, align 4
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ret i32 %6
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}
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define spir_func noundef i32 @no_attr_switch(i32 noundef %X) {
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; CHECK-LABEL: ; -- Begin function no_attr_switch
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; CHECK: OpSelectionMerge %[[#]] None
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entry:
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%X.addr = alloca i32, align 4
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%resp = alloca i32, align 4
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store i32 %X, ptr %X.addr, align 4
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%0 = load i32, ptr %X.addr, align 4
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switch i32 %0, label %sw.epilog [
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i32 0, label %sw.bb
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i32 1, label %sw.bb1
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i32 2, label %sw.bb2
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]
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sw.bb: ; preds = %entry
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%1 = load i32, ptr %X.addr, align 4
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%sub = sub nsw i32 0, %1
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store i32 %sub, ptr %resp, align 4
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br label %sw.epilog
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sw.bb1: ; preds = %entry
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%2 = load i32, ptr %X.addr, align 4
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%3 = load i32, ptr %X.addr, align 4
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%add = add nsw i32 %2, %3
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store i32 %add, ptr %resp, align 4
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br label %sw.epilog
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sw.bb2: ; preds = %entry
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%4 = load i32, ptr %X.addr, align 4
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%5 = load i32, ptr %X.addr, align 4
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%mul = mul nsw i32 %4, %5
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store i32 %mul, ptr %resp, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %entry, %sw.bb2, %sw.bb1, %sw.bb
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%6 = load i32, ptr %resp, align 4
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ret i32 %6
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}
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!0 = !{!"hlsl.controlflow.hint", i32 1}
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!1 = !{!"hlsl.controlflow.hint", i32 2}
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