6c32a1fdf7
Enable MachineCombining for FP add, sub and mul.
In order for this to work, the default instruction selection of reg/mem opcodes is disabled for ISD nodes that carry the flags that allow reassociation. The reg/mem folding is instead done after MachineCombiner by PeepholeOptimizer. SystemZInstrInfo optimizeLoadInstr() and foldMemoryOperandImpl() ("LoadMI version") have been implemented for this purpose also by this patch.
135 lines
3.8 KiB
LLVM
135 lines
3.8 KiB
LLVM
; Test 64-bit floating-point addition.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \
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; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs | FileCheck %s
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declare double @foo()
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; Check register addition.
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define double @f1(double %f1, double %f2) {
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; CHECK-LABEL: f1:
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; CHECK: adbr %f0, %f2
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; CHECK: br %r14
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%res = fadd double %f1, %f2
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ret double %res
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}
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; Check the low end of the ADB range.
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define double @f2(double %f1, ptr %ptr) {
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; CHECK-LABEL: f2:
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; CHECK: adb %f0, 0(%r2)
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; CHECK: br %r14
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%f2 = load double, ptr %ptr
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%res = fadd double %f1, %f2
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ret double %res
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}
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; Check the high end of the aligned ADB range.
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define double @f3(double %f1, ptr %base) {
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; CHECK-LABEL: f3:
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; CHECK: adb %f0, 4088(%r2)
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; CHECK: br %r14
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%ptr = getelementptr double, ptr %base, i64 511
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%f2 = load double, ptr %ptr
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%res = fadd double %f1, %f2
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ret double %res
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}
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; Check the next doubleword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define double @f4(double %f1, ptr %base) {
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; CHECK-LABEL: f4:
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; CHECK: aghi %r2, 4096
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; CHECK: adb %f0, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr double, ptr %base, i64 512
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%f2 = load double, ptr %ptr
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%res = fadd double %f1, %f2
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ret double %res
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}
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; Check negative displacements, which also need separate address logic.
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define double @f5(double %f1, ptr %base) {
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; CHECK-LABEL: f5:
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; CHECK: aghi %r2, -8
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; CHECK: adb %f0, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr double, ptr %base, i64 -1
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%f2 = load double, ptr %ptr
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%res = fadd double %f1, %f2
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ret double %res
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}
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; Check that ADB allows indices.
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define double @f6(double %f1, ptr %base, i64 %index) {
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; CHECK-LABEL: f6:
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; CHECK: sllg %r1, %r3, 3
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; CHECK: adb %f0, 800(%r1,%r2)
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; CHECK: br %r14
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%ptr1 = getelementptr double, ptr %base, i64 %index
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%ptr2 = getelementptr double, ptr %ptr1, i64 100
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%f2 = load double, ptr %ptr2
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%res = fadd double %f1, %f2
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ret double %res
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}
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; Check that additions of spilled values can use ADB rather than ADBR.
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define double @f7(ptr %ptr0) {
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; CHECK-LABEL: f7:
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; CHECK: brasl %r14, foo@PLT
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; CHECK-SCALAR: adb %f0, 160(%r15)
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; CHECK: br %r14
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%ptr1 = getelementptr double, ptr %ptr0, i64 2
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%ptr2 = getelementptr double, ptr %ptr0, i64 4
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%ptr3 = getelementptr double, ptr %ptr0, i64 6
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%ptr4 = getelementptr double, ptr %ptr0, i64 8
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%ptr5 = getelementptr double, ptr %ptr0, i64 10
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%ptr6 = getelementptr double, ptr %ptr0, i64 12
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%ptr7 = getelementptr double, ptr %ptr0, i64 14
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%ptr8 = getelementptr double, ptr %ptr0, i64 16
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%ptr9 = getelementptr double, ptr %ptr0, i64 18
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%ptr10 = getelementptr double, ptr %ptr0, i64 20
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%val0 = load double, ptr %ptr0
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%val1 = load double, ptr %ptr1
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%val2 = load double, ptr %ptr2
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%val3 = load double, ptr %ptr3
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%val4 = load double, ptr %ptr4
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%val5 = load double, ptr %ptr5
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%val6 = load double, ptr %ptr6
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%val7 = load double, ptr %ptr7
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%val8 = load double, ptr %ptr8
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%val9 = load double, ptr %ptr9
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%val10 = load double, ptr %ptr10
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%ret = call double @foo()
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%add0 = fadd double %ret, %val0
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%add1 = fadd double %add0, %val1
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%add2 = fadd double %add1, %val2
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%add3 = fadd double %add2, %val3
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%add4 = fadd double %add3, %val4
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%add5 = fadd double %add4, %val5
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%add6 = fadd double %add5, %val6
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%add7 = fadd double %add6, %val7
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%add8 = fadd double %add7, %val8
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%add9 = fadd double %add8, %val9
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%add10 = fadd double %add9, %val10
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ret double %add10
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}
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; Check that reassociation flags do not get in the way of ADB.
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define double @f8(ptr %x) {
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; CHECK-LABEL: f8:
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; CHECK: ld %f0
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; CHECK: adb %f0
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; CHECK: br %r14
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entry:
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%0 = load double, ptr %x, align 8
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%arrayidx1 = getelementptr inbounds double, ptr %x, i64 1
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%1 = load double, ptr %arrayidx1, align 8
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%add = fadd reassoc nsz arcp contract afn double %1, %0
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ret double %add
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}
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