Kalle Raiskila 8b2f70125f Make SPU backend handle insertelement and ...

store for "half vectors"

llvm-svn: 110198

2010-08-04 13:59:48 +00:00

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useful-harnesses

Teach lit that the .c files in 'test/CodeGen/CellSPU/useful-harnesses' aren't tests.

2009-10-19 03:53:55 +00:00

2009-01-01-BrCond.ll

Revert the main portion of r31856. It was causing BranchFolding

2009-10-22 00:03:58 +00:00

2010-04-07-DbgValueOtherTargets.ll

Split big test into multiple directories to cater to

2010-04-07 20:43:35 +00:00

and_ops.ll

Revert this dag combine change:

2009-12-17 00:40:05 +00:00

bigstack.ll

From Kalle Raiskila:

2010-03-29 17:38:47 +00:00

bss.ll

Make sure this test tests something.

2010-04-09 19:03:31 +00:00

call_indirect.ll

Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.

2010-07-16 04:45:42 +00:00

call.ll

Mark the SPU 'lr' instruction to never have side effects.

2010-06-21 15:08:16 +00:00

crash.ll

teach cellspu how to return i8 and i16 from calls,

2010-04-20 05:36:09 +00:00

ctpop.ll

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dg.exp

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dp_farith.ll

Delete useless trailing semicolons.

2010-01-05 17:55:26 +00:00

eqv.ll

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extract_elt.ll

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fcmp32.ll

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fcmp64.ll

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fdiv.ll

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fneg-fabs.ll

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i8ops.ll

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i64ops.ll

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icmp8.ll

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icmp16.ll

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icmp32.ll

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icmp64.ll

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immed16.ll

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immed32.ll

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immed64.ll

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int2fp.ll

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intrinsics_branch.ll

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intrinsics_float.ll

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intrinsics_logical.ll

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jumptable.ll

Mark the SPU 'lr' instruction to never have side effects.

2010-06-21 15:08:16 +00:00

loads.ll

Fix some tests that didn't test anything.

2010-06-26 20:05:06 +00:00

mul_ops.ll

Teach dag combine to fold the following transformation more aggressively:

2010-01-06 19:38:29 +00:00

mul-with-overflow.ll

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nand.ll

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or_ops.ll

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private.ll

Delete useless trailing semicolons.

2010-01-05 17:55:26 +00:00

rotate_ops.ll

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select_bits.ll

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sext128.ll

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shift_ops.ll

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shuffles.ll

Add the check to the testcase of r106419.

2010-06-21 15:11:51 +00:00

sp_farith.ll

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stores.ll

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storestruct.ll

"on the rare occasion the SPU BE produces illegal assembly - it tries to emit an add instruction of the form 'a reg, reg, imm'."

2010-05-04 17:58:46 +00:00

struct_1.ll

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sub_ops.ll

Fix encoding of 'sf' and 'sfh' instructions.

2010-05-10 08:13:49 +00:00

trunc.ll

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v2f32.ll

Make SPU backend handle insertelement and

2010-08-04 13:59:48 +00:00

v2i32.ll

Make SPU backend handle insertelement and

2010-08-04 13:59:48 +00:00

vec_const.ll

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vecinsert.ll

Fix SPU to cope with vector insertelement to an undef position.

2010-06-09 09:58:17 +00:00