6599fdab2c
The DXIL Prepare pass handles the IR mutations required to convert modern LLVM IR into something that more closely resembles LLVM-3.7 IR so that the DXIL bitcode writer can emit 3.7 IR. This change adds the codegen pass handling the first two IR transformations: * stripping new function attributes * converting fneg into fsub Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D122081
127 lines
4.5 KiB
C++
127 lines
4.5 KiB
C++
//===- DXILPrepare.cpp - Prepare LLVM Module for DXIL encoding ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file This file contains pases and utilities to convert a modern LLVM
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/// module into a module compatible with the LLVM 3.7-based DirectX Intermediate
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/// Language (DXIL).
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//===----------------------------------------------------------------------===//
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#include "DirectX.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/Module.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Compiler.h"
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#define DEBUG_TYPE "dxil-prepare"
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using namespace llvm;
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namespace {
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constexpr bool isValidForDXIL(Attribute::AttrKind Attr) {
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return is_contained({Attribute::Alignment,
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Attribute::AlwaysInline,
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Attribute::Builtin,
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Attribute::ByVal,
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Attribute::InAlloca,
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Attribute::Cold,
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Attribute::Convergent,
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Attribute::InlineHint,
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Attribute::InReg,
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Attribute::JumpTable,
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Attribute::MinSize,
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Attribute::Naked,
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Attribute::Nest,
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Attribute::NoAlias,
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Attribute::NoBuiltin,
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Attribute::NoCapture,
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Attribute::NoDuplicate,
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Attribute::NoImplicitFloat,
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Attribute::NoInline,
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Attribute::NonLazyBind,
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Attribute::NonNull,
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Attribute::Dereferenceable,
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Attribute::DereferenceableOrNull,
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Attribute::NoRedZone,
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Attribute::NoReturn,
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Attribute::NoUnwind,
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Attribute::OptimizeForSize,
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Attribute::OptimizeNone,
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Attribute::ReadNone,
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Attribute::ReadOnly,
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Attribute::ArgMemOnly,
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Attribute::Returned,
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Attribute::ReturnsTwice,
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Attribute::SExt,
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Attribute::StackAlignment,
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Attribute::StackProtect,
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Attribute::StackProtectReq,
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Attribute::StackProtectStrong,
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Attribute::SafeStack,
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Attribute::StructRet,
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Attribute::SanitizeAddress,
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Attribute::SanitizeThread,
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Attribute::SanitizeMemory,
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Attribute::UWTable,
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Attribute::ZExt},
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Attr);
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}
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class DXILPrepareModule : public ModulePass {
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public:
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bool runOnModule(Module &M) override {
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AttributeMask AttrMask;
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for (Attribute::AttrKind I = Attribute::None; I != Attribute::EndAttrKinds;
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I = Attribute::AttrKind(I + 1)) {
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if (!isValidForDXIL(I))
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AttrMask.addAttribute(I);
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}
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for (auto &F : M.functions()) {
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F.removeFnAttrs(AttrMask);
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F.removeRetAttrs(AttrMask);
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for (size_t Idx = 0; Idx < F.arg_size(); ++Idx)
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F.removeParamAttrs(Idx, AttrMask);
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for (auto &BB : F) {
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IRBuilder<> Builder(&BB);
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for (auto &I : make_early_inc_range(BB)) {
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if (I.getOpcode() == Instruction::FNeg) {
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Builder.SetInsertPoint(&I);
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Value *In = I.getOperand(0);
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Value *Zero = ConstantFP::get(In->getType(), -0.0);
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I.replaceAllUsesWith(Builder.CreateFSub(Zero, In));
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I.eraseFromParent();
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}
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}
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}
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}
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return true;
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}
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DXILPrepareModule() : ModulePass(ID) {}
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static char ID; // Pass identification.
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};
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char DXILPrepareModule::ID = 0;
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} // end anonymous namespace
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INITIALIZE_PASS_BEGIN(DXILPrepareModule, DEBUG_TYPE, "DXIL Prepare Module",
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false, false)
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INITIALIZE_PASS_END(DXILPrepareModule, DEBUG_TYPE, "DXIL Prepare Module", false,
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false)
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ModulePass *llvm::createDXILPrepareModulePass() {
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return new DXILPrepareModule();
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}
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