449f2f7140
PowerPC has its custom scheduler heuristic. It calls parent classes' tryCandidate in override version, but the function returns void, so this way doesn't actually help. This patch duplicates code from base scheduler into PPC machine scheduler class, which does what we wanted. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D94464
248 lines
9.0 KiB
C++
248 lines
9.0 KiB
C++
//===- PPCMachineScheduler.cpp - MI Scheduler for PowerPC -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "PPCMachineScheduler.h"
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#include "MCTargetDesc/PPCMCTargetDesc.h"
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using namespace llvm;
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static cl::opt<bool>
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DisableAddiLoadHeuristic("disable-ppc-sched-addi-load",
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cl::desc("Disable scheduling addi instruction before"
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"load for ppc"), cl::Hidden);
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static cl::opt<bool>
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EnableAddiHeuristic("ppc-postra-bias-addi",
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cl::desc("Enable scheduling addi instruction as early"
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"as possible post ra"),
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cl::Hidden, cl::init(true));
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static bool isADDIInstr(const GenericScheduler::SchedCandidate &Cand) {
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return Cand.SU->getInstr()->getOpcode() == PPC::ADDI ||
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Cand.SU->getInstr()->getOpcode() == PPC::ADDI8;
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}
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bool PPCPreRASchedStrategy::biasAddiLoadCandidate(SchedCandidate &Cand,
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SchedCandidate &TryCand,
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SchedBoundary &Zone) const {
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if (DisableAddiLoadHeuristic)
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return false;
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SchedCandidate &FirstCand = Zone.isTop() ? TryCand : Cand;
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SchedCandidate &SecondCand = Zone.isTop() ? Cand : TryCand;
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if (isADDIInstr(FirstCand) && SecondCand.SU->getInstr()->mayLoad()) {
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TryCand.Reason = Stall;
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return true;
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}
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if (FirstCand.SU->getInstr()->mayLoad() && isADDIInstr(SecondCand)) {
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TryCand.Reason = NoCand;
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return true;
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}
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return false;
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}
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void PPCPreRASchedStrategy::tryCandidate(SchedCandidate &Cand,
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SchedCandidate &TryCand,
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SchedBoundary *Zone) const {
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// From GenericScheduler::tryCandidate
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// Initialize the candidate if needed.
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if (!Cand.isValid()) {
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TryCand.Reason = NodeOrder;
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return;
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}
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// Bias PhysReg Defs and copies to their uses and defined respectively.
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if (tryGreater(biasPhysReg(TryCand.SU, TryCand.AtTop),
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biasPhysReg(Cand.SU, Cand.AtTop), TryCand, Cand, PhysReg))
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return;
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// Avoid exceeding the target's limit.
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if (DAG->isTrackingPressure() &&
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tryPressure(TryCand.RPDelta.Excess, Cand.RPDelta.Excess, TryCand, Cand,
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RegExcess, TRI, DAG->MF))
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return;
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// Avoid increasing the max critical pressure in the scheduled region.
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if (DAG->isTrackingPressure() &&
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tryPressure(TryCand.RPDelta.CriticalMax, Cand.RPDelta.CriticalMax,
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TryCand, Cand, RegCritical, TRI, DAG->MF))
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return;
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// We only compare a subset of features when comparing nodes between
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// Top and Bottom boundary. Some properties are simply incomparable, in many
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// other instances we should only override the other boundary if something
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// is a clear good pick on one boundary. Skip heuristics that are more
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// "tie-breaking" in nature.
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bool SameBoundary = Zone != nullptr;
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if (SameBoundary) {
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// For loops that are acyclic path limited, aggressively schedule for
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// latency. Within an single cycle, whenever CurrMOps > 0, allow normal
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// heuristics to take precedence.
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if (Rem.IsAcyclicLatencyLimited && !Zone->getCurrMOps() &&
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tryLatency(TryCand, Cand, *Zone))
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return;
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// Prioritize instructions that read unbuffered resources by stall cycles.
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if (tryLess(Zone->getLatencyStallCycles(TryCand.SU),
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Zone->getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall))
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return;
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}
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// Keep clustered nodes together to encourage downstream peephole
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// optimizations which may reduce resource requirements.
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//
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// This is a best effort to set things up for a post-RA pass. Optimizations
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// like generating loads of multiple registers should ideally be done within
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// the scheduler pass by combining the loads during DAG postprocessing.
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const SUnit *CandNextClusterSU =
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Cand.AtTop ? DAG->getNextClusterSucc() : DAG->getNextClusterPred();
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const SUnit *TryCandNextClusterSU =
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TryCand.AtTop ? DAG->getNextClusterSucc() : DAG->getNextClusterPred();
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if (tryGreater(TryCand.SU == TryCandNextClusterSU,
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Cand.SU == CandNextClusterSU, TryCand, Cand, Cluster))
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return;
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if (SameBoundary) {
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// Weak edges are for clustering and other constraints.
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if (tryLess(getWeakLeft(TryCand.SU, TryCand.AtTop),
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getWeakLeft(Cand.SU, Cand.AtTop), TryCand, Cand, Weak))
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return;
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}
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// Avoid increasing the max pressure of the entire region.
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if (DAG->isTrackingPressure() &&
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tryPressure(TryCand.RPDelta.CurrentMax, Cand.RPDelta.CurrentMax, TryCand,
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Cand, RegMax, TRI, DAG->MF))
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return;
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if (SameBoundary) {
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// Avoid critical resource consumption and balance the schedule.
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TryCand.initResourceDelta(DAG, SchedModel);
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if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
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TryCand, Cand, ResourceReduce))
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return;
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if (tryGreater(TryCand.ResDelta.DemandedResources,
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Cand.ResDelta.DemandedResources, TryCand, Cand,
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ResourceDemand))
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return;
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// Avoid serializing long latency dependence chains.
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// For acyclic path limited loops, latency was already checked above.
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if (!RegionPolicy.DisableLatencyHeuristic && TryCand.Policy.ReduceLatency &&
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!Rem.IsAcyclicLatencyLimited && tryLatency(TryCand, Cand, *Zone))
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return;
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// Fall through to original instruction order.
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if ((Zone->isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum) ||
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(!Zone->isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) {
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TryCand.Reason = NodeOrder;
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}
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}
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// GenericScheduler::tryCandidate end
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// Add powerpc specific heuristic only when TryCand isn't selected or
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// selected as node order.
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if (TryCand.Reason != NodeOrder && TryCand.Reason != NoCand)
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return;
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// There are some benefits to schedule the ADDI before the load to hide the
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// latency, as RA may create a true dependency between the load and addi.
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if (SameBoundary) {
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if (biasAddiLoadCandidate(Cand, TryCand, *Zone))
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return;
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}
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}
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bool PPCPostRASchedStrategy::biasAddiCandidate(SchedCandidate &Cand,
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SchedCandidate &TryCand) const {
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if (!EnableAddiHeuristic)
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return false;
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if (isADDIInstr(TryCand) && !isADDIInstr(Cand)) {
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TryCand.Reason = Stall;
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return true;
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}
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return false;
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}
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void PPCPostRASchedStrategy::tryCandidate(SchedCandidate &Cand,
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SchedCandidate &TryCand) {
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// From PostGenericScheduler::tryCandidate
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// Initialize the candidate if needed.
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if (!Cand.isValid()) {
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TryCand.Reason = NodeOrder;
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return;
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}
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// Prioritize instructions that read unbuffered resources by stall cycles.
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if (tryLess(Top.getLatencyStallCycles(TryCand.SU),
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Top.getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall))
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return;
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// Keep clustered nodes together.
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if (tryGreater(TryCand.SU == DAG->getNextClusterSucc(),
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Cand.SU == DAG->getNextClusterSucc(), TryCand, Cand, Cluster))
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return;
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// Avoid critical resource consumption and balance the schedule.
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if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
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TryCand, Cand, ResourceReduce))
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return;
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if (tryGreater(TryCand.ResDelta.DemandedResources,
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Cand.ResDelta.DemandedResources, TryCand, Cand,
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ResourceDemand))
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return;
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// Avoid serializing long latency dependence chains.
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if (Cand.Policy.ReduceLatency && tryLatency(TryCand, Cand, Top)) {
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return;
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}
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// Fall through to original instruction order.
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if (TryCand.SU->NodeNum < Cand.SU->NodeNum)
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TryCand.Reason = NodeOrder;
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// PostGenericScheduler::tryCandidate end
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// Add powerpc post ra specific heuristic only when TryCand isn't selected or
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// selected as node order.
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if (TryCand.Reason != NodeOrder && TryCand.Reason != NoCand)
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return;
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// There are some benefits to schedule the ADDI as early as possible post ra
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// to avoid stalled by vector instructions which take up all the hw units.
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// And ADDI is usually used to post inc the loop indvar, which matters the
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// performance.
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if (biasAddiCandidate(Cand, TryCand))
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return;
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}
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void PPCPostRASchedStrategy::enterMBB(MachineBasicBlock *MBB) {
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// Custom PPC PostRA specific behavior here.
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PostGenericScheduler::enterMBB(MBB);
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}
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void PPCPostRASchedStrategy::leaveMBB() {
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// Custom PPC PostRA specific behavior here.
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PostGenericScheduler::leaveMBB();
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}
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void PPCPostRASchedStrategy::initialize(ScheduleDAGMI *Dag) {
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// Custom PPC PostRA specific initialization here.
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PostGenericScheduler::initialize(Dag);
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}
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SUnit *PPCPostRASchedStrategy::pickNode(bool &IsTopNode) {
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// Custom PPC PostRA specific scheduling here.
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return PostGenericScheduler::pickNode(IsTopNode);
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}
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