Files
clang-p2996/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxExt.mir
Min-Yih Hsu c23a780c30 [M68k][test](6/8) Add all of the tests
And a small utilities -- extract-section.py -- that helps extracting
specific object file section and printing in textual format. This
utility is just a workaround for tests inside `Encoding`. Hopefully in
the future we can replace dependencies in those tests with existing tools
(e.g. llvm-readobj). Please refer to this bug for more context:
https://bugs.llvm.org/show_bug.cgi?id=49245

Note that since we don't have AsmParser for now, we are testing the MC
part using MIR as input and put those tests under the `Encoding` folder.
In the future when AsmParser (and disassembler) is finished, those tests
will be moved to `test/MC/M68k`.

Authors: myhsu, m4yers, glaubitz

Differential Revision: https://reviews.llvm.org/D88392
2021-03-08 12:30:57 -08:00

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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=EXT16,EXT32
#------------------------------------------------------------------------------
# MxExt sign extends data inside a register
#------------------------------------------------------------------------------
# ---------------------------------------------------------------
# F E D C B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------------------------------------------------------
# 0 1 0 0 1 0 0 | OPMODE | 0 0 0 | REG
# ---------------------------------------------------------------
# EXT16: 0 1 0 0 1 0 0 0 . 1 0 0 0 0 0 0 0
# EXT16-SAME: 0 1 0 0 1 0 0 0 . 1 0 0 0 0 0 1 1
# EXT32-SAME: 0 1 0 0 1 0 0 0 . 1 1 0 0 0 0 0 0
# EXT32-SAME: 0 1 0 0 1 0 0 0 . 1 1 0 0 0 1 1 1
name: MxEXT
body: |
bb.0:
$wd0 = EXT16 $wd0, implicit-def $ccr
$wd3 = EXT16 $wd3, implicit-def $ccr
$d0 = EXT32 $d0, implicit-def $ccr
$d7 = EXT32 $d7, implicit-def $ccr