2b50ce1524
This patch adds support for the default AltiVec ABI for AIX. Vector registers 20 through 31 are marked as reserved and cannot be used in the default ABI. This patch adds handling for this case and also remove the default AltiVec ABI errors. Reviewed By: sfertile Differential Revision: https://reviews.llvm.org/D96351
202 lines
7.9 KiB
LLVM
202 lines
7.9 KiB
LLVM
; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs -mcpu=pwr7 \
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; RUN: -mattr=+altivec -stop-after=prologepilog < %s | \
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; RUN: FileCheck --check-prefix=MIR32 %s
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; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
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; RUN: -mcpu=pwr7 -mattr=+altivec < %s | \
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; RUN: FileCheck --check-prefix=ASM32 %s
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; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -verify-machineinstrs \
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; RUN: -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \
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; RUN: FileCheck --check-prefix=MIR64 %s
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; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -verify-machineinstrs \
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; RUN: -mcpu=pwr7 -mattr=+altivec < %s | \
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; RUN: FileCheck --check-prefix=ASM64 %s
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define dso_local void @vec_regs() {
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entry:
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call void asm sideeffect "", "~{v13},~{v20},~{v26},~{v31}"()
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ret void
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}
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; MIR32-LABEL: name: vec_regs
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; MIR32: fixedStack: []
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; MIR32-NOT: STXVD2X killed $v20
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; MIR32-NOT: STXVD2X killed $v26
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; MIR32-NOT: STXVD2X killed $v31
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; MIR32-LABEL: INLINEASM
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; MIR32-NOT: $v20 = LXVD2X
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; MIR32-NOT: $v26 = LXVD2X
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; MIR32-NOT: $v31 = LXVD2X
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; MIR32: BLR implicit $lr, implicit $rm
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; MIR64-LABEL: name: vec_regs
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; MIR64: fixedStack: []
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; MIR64-NOT: STXVD2X killed $v20
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; MIR64-NOT: STXVD2X killed $v26
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; MIR64-NOT: STXVD2X killed $v31
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; MIR64-LABEL: INLINEASM
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; MIR64-NOT: $v20 = LXVD2X
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; MIR64-NOT: $v26 = LXVD2X
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; MIR64-NOT: $v31 = LXVD2X
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; MIR64: BLR8 implicit $lr8, implicit $rm
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; ASM32-LABEL: .vec_regs:
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; ASM32-NOT: 20
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; ASM32-NOT: 26
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; ASM32-NOT: 31
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; ASM32-DAG: #APP
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; ASM32-DAG: #NO_APP
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; ASM32: blr
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; ASM64-LABEL: .vec_regs:
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; ASM64-NOT: 20
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; ASM64-NOT: 26
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; ASM64-NOT: 31
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; ASM64-DAG: #APP
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; ASM64-DAG: #NO_APP
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; ASM64: blr
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define dso_local void @fprs_gprs_vecregs() {
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call void asm sideeffect "", "~{r14},~{r25},~{r31},~{f14},~{f21},~{f31},~{v20},~{v26},~{v31}"()
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ret void
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}
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; MIR32-LABEL: name: fprs_gprs_vecregs
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; MIR32: fixedStack:
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; MIR32: liveins: $r14, $r25, $r31, $f14, $f21, $f31
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; MIR32-NOT: STXVD2X killed $v20
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; MIR32-NOT: STXVD2X killed $v26
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; MIR32-NOT: STXVD2X killed $v31
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; MIR32-DAG: STW killed $r14, -216, $r1 :: (store 4 into %fixed-stack.5, align 8)
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; MIR32-DAG: STW killed $r25, -172, $r1 :: (store 4 into %fixed-stack.4)
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; MIR32-DAG: STW killed $r31, -148, $r1 :: (store 4 into %fixed-stack.3)
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; MIR32-DAG: STFD killed $f14, -144, $r1 :: (store 8 into %fixed-stack.2, align 16)
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; MIR32-DAG: STFD killed $f21, -88, $r1 :: (store 8 into %fixed-stack.1)
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; MIR32-DAG: STFD killed $f31, -8, $r1 :: (store 8 into %fixed-stack.0)
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; MIR32-LABEL: INLINEASM
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; MIR32-NOT: $v20 = LXVD2X
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; MIR32-NOT: $v26 = LXVD2X
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; MIR32-NOT: $v31 = LXVD2X
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; MIR32-DAG: $r14 = LWZ -216, $r1 :: (load 4 from %fixed-stack.5, align 8)
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; MIR32-DAG: $r25 = LWZ -172, $r1 :: (load 4 from %fixed-stack.4)
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; MIR32-DAG: $r31 = LWZ -148, $r1 :: (load 4 from %fixed-stack.3)
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; MIR32-DAG: $f14 = LFD -144, $r1 :: (load 8 from %fixed-stack.2, align 16)
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; MIR32-DAG: $f21 = LFD -88, $r1 :: (load 8 from %fixed-stack.1)
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; MIR32-DAG: $f31 = LFD -8, $r1 :: (load 8 from %fixed-stack.0)
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; MIR32-DAG: BLR implicit $lr, implicit $rm
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; MIR64-LABEL: name: fprs_gprs_vecregs
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; MIR64: fixedStack:
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; MIR64: liveins: $x14, $x25, $x31, $f14, $f21, $f31
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; MIR64-NOT: STXVD2X killed $v20
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; MIR64-NOT: STXVD2X killed $v26
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; MIR64-NOT: STXVD2X killed $v31
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; MIR64-DAG: STD killed $x14, -288, $x1 :: (store 8 into %fixed-stack.5, align 16)
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; MIR64-DAG: STD killed $x25, -200, $x1 :: (store 8 into %fixed-stack.4)
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; MIR64-DAG: STD killed $x31, -152, $x1 :: (store 8 into %fixed-stack.3)
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; MIR64-DAG: STFD killed $f14, -144, $x1 :: (store 8 into %fixed-stack.2, align 16)
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; MIR64-DAG: STFD killed $f21, -88, $x1 :: (store 8 into %fixed-stack.1)
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; MIR64-DAG: STFD killed $f31, -8, $x1 :: (store 8 into %fixed-stack.0)
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; MIR64-LABEL: INLINEASM
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; MIR64-NOT: $v20 = LXVD2X
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; MIR64-NOT: $v26 = LXVD2X
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; MIR64-NOT: $v31 = LXVD2X
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; MIR64-DAG: $x14 = LD -288, $x1 :: (load 8 from %fixed-stack.5, align 16)
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; MIR64-DAG: $x25 = LD -200, $x1 :: (load 8 from %fixed-stack.4)
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; MIR64-DAG: $x31 = LD -152, $x1 :: (load 8 from %fixed-stack.3)
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; MIR64-DAG: $f14 = LFD -144, $x1 :: (load 8 from %fixed-stack.2, align 16)
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; MIR64-DAG: $f21 = LFD -88, $x1 :: (load 8 from %fixed-stack.1)
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; MIR64-DAG: $f31 = LFD -8, $x1 :: (load 8 from %fixed-stack.0)
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; MIR64: BLR8 implicit $lr8, implicit $rm
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;; We don't have -ppc-full-reg-names on AIX so can't reliably check-not for
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;; only vector registers numbers in this case.
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; ASM32-LABEL: .fprs_gprs_vecregs:
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; ASM32-DAG: stw 14, -216(1) # 4-byte Folded Spill
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; ASM32-DAG: stw 25, -172(1) # 4-byte Folded Spill
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; ASM32-DAG: stw 31, -148(1) # 4-byte Folded Spill
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; ASM32-DAG: stfd 14, -144(1) # 8-byte Folded Spill
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; ASM32-DAG: stfd 21, -88(1) # 8-byte Folded Spill
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; ASM32-DAG: stfd 31, -8(1) # 8-byte Folded Spill
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; ASM32-DAG: #APP
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; ASM32-DAG: #NO_APP
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; ASM32-DAG: lfd 31, -8(1) # 8-byte Folded Reload
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; ASM32-DAG: lfd 21, -88(1) # 8-byte Folded Reload
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; ASM32-DAG: lfd 14, -144(1) # 8-byte Folded Reload
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; ASM32-DAG: lwz 31, -148(1) # 4-byte Folded Reload
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; ASM32-DAG: lwz 25, -172(1) # 4-byte Folded Reload
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; ASM32-DAG: lwz 14, -216(1) # 4-byte Folded Reload
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; ASM32: blr
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; ASM64-LABEL .fprs_gprs_vecregs:
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; ASM64-DAG: std 14, -288(1) # 8-byte Folded Spill
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; ASM64-DAG: std 25, -200(1) # 8-byte Folded Spill
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; ASM64-DAG: std 31, -152(1) # 8-byte Folded Spill
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; ASM64-DAG: stfd 14, -144(1) # 8-byte Folded Spill
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; ASM64-DAG: stfd 21, -88(1) # 8-byte Folded Spill
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; ASM64-DAG: stfd 31, -8(1) # 8-byte Folded Spill
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; ASM64-DAG: #APP
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; ASM64-DAG: #NO_APP
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; ASM64-DAG: lfd 31, -8(1) # 8-byte Folded Reload
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; ASM64-DAG: lfd 21, -88(1) # 8-byte Folded Reload
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; ASM64-DAG: lfd 14, -144(1) # 8-byte Folded Reload
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; ASM64-DAG: ld 31, -152(1) # 8-byte Folded Reload
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; ASM64-DAG: ld 25, -200(1) # 8-byte Folded Reload
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; ASM64-DAG: ld 14, -288(1) # 8-byte Folded Reload
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; ASM64: blr
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define dso_local void @all_fprs_and_vecregs() {
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call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6}~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19}"()
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ret void
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}
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;; Check that reserved vectors are not used.
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; MIR32-LABEL: all_fprs_and_vecregs
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; MIR32-NOT: $v20
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; MIR32-NOT: $v21
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; MIR32-NOT: $v22
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; MIR32-NOT: $v23
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; MIR32-NOT: $v24
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; MIR32-NOT: $v25
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; MIR32-NOT: $v26
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; MIR32-NOT: $v27
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; MIR32-NOT: $v28
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; MIR32-NOT: $v29
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; MIR32-NOT: $v30
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; MIR32-NOT: $v31
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; MIR64-LABEL: all_fprs_and_vecregs
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; MIR64-NOT: $v20
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; MIR64-NOT: $v21
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; MIR64-NOT: $v22
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; MIR64-NOT: $v23
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; MIR64-NOT: $v24
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; MIR64-NOT: $v25
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; MIR64-NOT: $v26
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; MIR64-NOT: $v27
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; MIR64-NOT: $v28
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; MIR64-NOT: $v29
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; MIR64-NOT: $v30
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; MIR64-NOT: $v31
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