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clang-p2996/llvm/test/CodeGen/RISCV
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Craig Topper 351844edf1 [RISCV] Add support for VECTOR_REVERSE for scalable vector types. 
I've left mask registers to a future patch as we'll need
to convert them to full vectors, shuffle, and then truncate.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D97609
2021-03-09 10:03:45 -08:00
..
GlobalISel
…
intrinsics
…
rvv
[RISCV] Add support for VECTOR_REVERSE for scalable vector types.
2021-03-09 10:03:45 -08:00
add-before-shl.ll
…
add-imm.ll
[RISCV] optimize addition with a pair of (addi imm)
2020-07-07 18:57:28 -07:00
addc-adde-sube-subc.ll
…
addcarry.ll
…
addimm-mulimm.ll
[RISCV][test] Add a test for (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) transformation
2020-07-10 18:33:12 -07:00
addrspacecast.ll
[RISCV] Assume no-op addrspacecasts by default
2020-12-18 21:03:37 +00:00
align.ll
…
alloca.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
alu8.ll
[RISCV] Don't print zext.b alias.
2021-01-05 10:41:08 -08:00
alu16.ll
[RISCV] Optimize (srl (and X, 0xffff), C) -> (srli (slli X, 16), 16 + C).
2021-02-01 09:37:55 -08:00
alu32.ll
…
alu64.ll
[RISCV] Add isel pattern to match (i64 (sra (shl X, 32), C)) to SRAIW if C > 32.
2020-11-25 21:57:48 -08:00
analyze-branch.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
arith-with-overflow.ll
…
atomic-cmpxchg-flag.ll
…
atomic-cmpxchg.ll
[RISCV] Copy isUnneededShiftMask from X86.
2021-01-27 20:46:10 -08:00
atomic-fence.ll
…
atomic-load-store.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
atomic-rmw.ll
[RISCV] Copy isUnneededShiftMask from X86.
2021-01-27 20:46:10 -08:00
attributes.ll
[RISCV] Update the version number to v0.10 for vector.
2021-01-30 07:20:05 +08:00
blockaddress.ll
[RISCV] Fix inaccurate annotations on PseudoBRIND
2020-08-21 11:38:42 +01:00
branch-relaxation.ll
[RISCV] Indirect branch generation in position independent code
2020-08-17 13:09:26 +01:00
branch.ll
[RISCV] Add isel pattern to match X > -1 to bgez.
2021-02-25 07:42:22 -08:00
bswap-ctlz-cttz-ctpop.ll
[RISCV] Optimize (srl (and X, 0xffff), C) -> (srli (slli X, 16), 16 + C).
2021-02-01 09:37:55 -08:00
byval.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
callee-saved-fpr32s.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
callee-saved-fpr64s.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
callee-saved-gprs.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-ilp32-ilp32f-common.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-ilp32.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-ilp32d.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-ilp32f-ilp32d-common.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-lp64-lp64f-common.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-lp64-lp64f-lp64d-common.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-lp64.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-rv32f-ilp32.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-sext-zext.ll
[RISCV] Don't print zext.b alias.
2021-01-05 10:41:08 -08:00
calls.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
cmp-bool.ll
[DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1)
2020-07-15 07:34:22 +00:00
codemodel-lowering.ll
[RISCV] Fix inaccurate annotations on PseudoBRIND
2020-08-21 11:38:42 +01:00
compress-float.ll
…
compress-inline-asm.ll
…
compress.ll
[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump
2020-12-04 10:34:12 -08:00
copy-frameindex.mir
[RISCV] Only return DestSourcePair from isCopyInstrImpl for registers
2020-11-03 03:55:47 +00:00
copysign-casts.ll
[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
2021-01-15 11:14:14 -08:00
disable-tail-calls.ll
…
disjoint.ll
…
div.ll
[TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on illegal types before type legalization if we can find a larger legal type that supports MUL.
2021-02-11 09:43:13 -08:00
double-arith.ll
[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
2020-11-25 15:07:34 -08:00
double-bitmanip-dagcombines.ll
…
double-br-fcmp.ll
[RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
2021-01-19 11:21:48 -08:00
double-calling-conv.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
double-convert.ll
[RISCV] Use bitsLE instead of strict == MVT::i32 in assertsexti32 and assertzexti32.
2021-01-24 13:58:14 -08:00
double-fcmp.ll
[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
2021-01-12 10:45:03 -08:00
double-frem.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
double-imm.ll
…
double-intrinsics.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
double-isnan.ll
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
double-mem.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
double-previous-failure.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
double-select-fcmp.ll
[RISCV] Optimize select_cc after fp compare expansion
2021-01-14 13:41:40 -08:00
double-stack-spill-restore.ll
[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper
2021-01-25 16:37:21 -08:00
dwarf-eh.ll
…
exception-pointer-register.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
fastcc-float.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
fastcc-int.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
fixups-diff.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
fixups-relax-diff.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
float-arith.ll
[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
2020-11-25 15:07:34 -08:00
float-bit-preserving-dagcombines.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
float-bitmanip-dagcombines.ll
…
float-br-fcmp.ll
[RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
2021-01-19 11:21:48 -08:00
float-convert.ll
[RISCV] Use bitsLE instead of strict == MVT::i32 in assertsexti32 and assertzexti32.
2021-01-24 13:58:14 -08:00
float-fcmp.ll
[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
2021-01-12 10:45:03 -08:00
float-frem.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
float-imm.ll
…
float-intrinsics.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
float-isnan.ll
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
float-mem.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
float-select-fcmp.ll
[RISCV] Optimize select_cc after fp compare expansion
2021-01-14 13:41:40 -08:00
flt-rounds.ll
…
fold-addi-loadstore.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
fp16-promote.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
fp128.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
fp-imm.ll
…
frame-info.ll
[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
2021-01-15 11:14:14 -08:00
frame.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
frameaddr-returnaddr.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
get-register-invalid.ll
…
get-register-noreserve.ll
…
get-register-reserve.ll
…
get-setcc-result-type.ll
…
ghccc-rv32.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
ghccc-rv64.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
half-arith.ll
[RISCV] Add additional half precision fnmadd/fnmsub tests with an fneg on the second operand instead of the first.
2020-12-02 21:13:42 -08:00
half-bitmanip-dagcombines.ll
[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
2021-01-15 11:14:14 -08:00
half-br-fcmp.ll
[RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
2021-01-19 11:21:48 -08:00
half-convert.ll
[RISCV] Use bitsLE instead of strict == MVT::i32 in assertsexti32 and assertzexti32.
2021-01-24 13:58:14 -08:00
half-fcmp.ll
[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
2021-01-12 10:45:03 -08:00
half-imm.ll
[RISCV] Support Zfh half-precision floating-point extension.
2020-12-03 09:16:33 +08:00
half-intrinsics.ll
[RISCV] Add f16 to isFMAFasterThanFMulAndFAdd now that the Zfh extension is supported
2020-12-02 20:31:43 -08:00
half-isnan.ll
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
half-mem.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
half-select-fcmp.ll
[RISCV] Optimize select_cc after fp compare expansion
2021-01-14 13:41:40 -08:00
hoist-global-addr-base.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
i32-icmp.ll
…
imm-cse.ll
…
imm.ll
[RISCV][NFC] Add more tests for 32-bit constant materialization
2020-10-22 11:36:34 +01:00
indirectbr.ll
[RISCV] Fix inaccurate annotations on PseudoBRIND
2020-08-21 11:38:42 +01:00
init-array.ll
…
inline-asm-abi-names.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
inline-asm-clobbers.ll
…
inline-asm-d-abi-names.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
inline-asm-d-constraint-f.ll
…
inline-asm-f-abi-names.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
inline-asm-f-constraint-f.ll
…
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
…
inline-asm.ll
[MC][RISCV] Set UseIntegratedAssembler to true
2020-07-12 21:04:48 -07:00
interrupt-attr-args-error.ll
…
interrupt-attr-callee.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
interrupt-attr-ret-error.ll
…
interrupt-attr.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
jumptable.ll
[RISCV] Basic jump table lowering
2020-12-22 15:05:54 +00:00
large-stack.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
legalize-fneg.ll
…
lit.local.cfg
…
lsr-legaladdimm.ll
…
machineoutliner.mir
…
mattr-invalid-combination.ll
…
mem64.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
mem.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
mir-target-flags.ll
[TargetMachine] Don't imply dso_local on function declarations in Reloc::Static model for ELF/wasm
2020-12-05 14:54:37 -08:00
module-target-abi2.ll
…
module-target-abi.ll
…
mul.ll
[RISCV] Optimize multiplication with constant
2021-01-09 10:37:21 +08:00
musttail-call.ll
OpaquePtr: Bulk update tests to use typed sret
2020-11-20 17:58:26 -05:00
neg-abs.ll
[RISCV][NFC] Increase test coverage of Zbt extension
2021-01-18 17:30:35 +00:00
nomerge.ll
…
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax.ll
…
option-rvc.ll
…
out-of-reach-emergency-slot.mir
[RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer
2021-01-23 09:10:03 +00:00
pic-models.ll
Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
2020-07-14 11:15:01 +01:00
pr40333.ll
…
prefetch.ll
…
readcyclecounter.ll
…
rem.ll
[RISCV] Add i8/i16 test cases to div.ll and i8/i16/i64 to rem.ll. NFC
2021-02-04 16:46:23 -08:00
remat.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
reserved-reg-errors.ll
…
reserved-regs.ll
…
rotl-rotr.ll
…
rv32e.ll
…
rv32i-rv64i-float-double.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
rv32i-rv64i-half.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
rv32Zba.ll
[RISCV] Add isel patterns for SH*ADD(.UW)
2021-01-22 13:28:41 -08:00
rv32Zbb.ll
[RISCV] Add support for rev8 and orc.b to Zbb.
2021-01-22 12:49:10 -08:00
rv32Zbbp.ll
[RISCV] Move pack instructions to Zbp extension only.
2021-01-22 12:49:10 -08:00
rv32Zbp.ll
[RISCV] Pre-commit test file changes from D96661. NFC
2021-02-18 09:29:36 -08:00
rv32Zbs.ll
[RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec.
2021-01-22 12:49:10 -08:00
rv32Zbt.ll
[RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec.
2021-01-22 12:49:10 -08:00
rv64-large-stack.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
rv64d-double-convert.ll
[RISCV] Use fcvt.h/d/f.w if the input is an assertsexti32 not just when the input is sext_inreg.
2020-12-04 18:40:02 -08:00
rv64f-float-convert.ll
[RISCV] Use fcvt.h/d/f.w if the input is an assertsexti32 not just when the input is sext_inreg.
2020-12-04 18:40:02 -08:00
rv64f-half-convert.ll
[RISCV] Use fcvt.h/d/f.w if the input is an assertsexti32 not just when the input is sext_inreg.
2020-12-04 18:40:02 -08:00
rv64i-complex-float.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
rv64i-demanded-bits.ll
[RISCV] Improve worklist management in the DAG combine for SLLW/SRLW/SRAW
2020-10-29 14:52:53 -07:00
rv64i-double-softfloat.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
rv64i-exhaustive-w-insts.ll
…
rv64i-single-softfloat.ll
[RISCV] Use sign extend for i32 arguments and returns in makeLibCall on RV64.
2021-01-25 09:33:48 -08:00
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
…
rv64m-exhaustive-w-insts.ll
[RISCV] Have sexti32 also recognize AssertZExt from types smaller than i32.
2021-02-22 14:56:22 -08:00
rv64m-w-insts-legalization.ll
Revert "[BPI] Improve static heuristics for integer comparisons"
2020-08-17 20:44:33 +02:00
rv64Zba.ll
[RISCV] Add isel patterns to optimize slli.uw patterns without Zba extension.
2021-01-25 16:12:08 -08:00
rv64Zbb.ll
[RISCV][LegalizeTypes] Try to expand BSWAP before promoting if the promoted BSWAP would expand anyway.
2021-01-31 14:33:29 -08:00
rv64Zbbp.ll
[RISCV] Move pack instructions to Zbp extension only.
2021-01-22 12:49:10 -08:00
rv64Zbp.ll
[RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64
2021-02-19 10:07:12 -08:00
rv64Zbs.ll
[RISCV] Remove isel patterns for Zbs *W instructions.
2021-01-28 09:33:56 -08:00
rv64Zbt.ll
Recommit "[RISCV] Legalize select when Zbt extension available"
2021-01-21 12:07:44 -08:00
sadd_sat_plus.ll
[RISCV] Fold (select_cc (xor X, Y), 0, eq/ne, trueV, falseV) -> (select_cc X, Y, eq/ne, trueV, falseV)
2021-03-07 09:29:55 -08:00
sadd_sat.ll
[RISCV] Fold (select_cc (xor X, Y), 0, eq/ne, trueV, falseV) -> (select_cc X, Y, eq/ne, trueV, falseV)
2021-03-07 09:29:55 -08:00
saverestore.ll
…
scalable-vector-struct.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
sdata-limit-0.ll
…
sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
…
select-and.ll
Recommit "[RISCV] Legalize select when Zbt extension available"
2021-01-21 12:07:44 -08:00
select-bare.ll
Recommit "[RISCV] Legalize select when Zbt extension available"
2021-01-21 12:07:44 -08:00
select-cc.ll
Recommit "[RISCV] Legalize select when Zbt extension available"
2021-01-21 12:07:44 -08:00
select-const.ll
Recommit "[RISCV] Legalize select when Zbt extension available"
2021-01-21 12:07:44 -08:00
select-optimize-multiple.ll
[RISCV] Add more cmov isel patterns to handle seteq/ne with a small non-zero immediate.
2021-01-22 14:51:22 -08:00
select-optimize-multiple.mir
[RISCV][NFC] Increase test coverage of Zbt extension
2021-01-18 17:30:35 +00:00
select-or.ll
Recommit "[RISCV] Legalize select when Zbt extension available"
2021-01-21 12:07:44 -08:00
setcc-logic.ll
[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper
2021-01-25 16:37:21 -08:00
sext-zext-trunc.ll
[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper
2021-01-25 16:37:21 -08:00
shadowcallstack.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
shift-masked-shamt.ll
[RISCV] Copy isUnneededShiftMask from X86.
2021-01-27 20:46:10 -08:00
shifts.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
shrinkwrap.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
spill-fpr-scalar.ll
[RISCV] Spilling for RISC-V V extension. (2nd version)
2021-02-17 14:05:19 +08:00
split-offsets.ll
…
split-sp-adjust.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
srem-lkk.ll
[TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on illegal types before type legalization if we can find a larger legal type that supports MUL.
2021-02-11 09:43:13 -08:00
srem-vector-lkk.ll
[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
2021-01-15 11:14:14 -08:00
ssub_sat_plus.ll
[RISCV] Fold (select_cc (xor X, Y), 0, eq/ne, trueV, falseV) -> (select_cc X, Y, eq/ne, trueV, falseV)
2021-03-07 09:29:55 -08:00
ssub_sat.ll
[RISCV] Fold (select_cc (xor X, Y), 0, eq/ne, trueV, falseV) -> (select_cc X, Y, eq/ne, trueV, falseV)
2021-03-07 09:29:55 -08:00
stack-realignment-with-variable-sized-objects.ll
[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
2021-01-15 11:14:14 -08:00
stack-realignment.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
stack-store-check.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
subtarget-features-std-ext.ll
…
tail-calls.ll
OpaquePtr: Bulk update tests to use typed sret
2020-11-20 17:58:26 -05:00
target-abi-invalid.ll
…
target-abi-valid.ll
…
thread-pointer.ll
…
tls-models.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
uadd_sat_plus.ll
[RISCV] Fold (select_cc (setlt X, Y), 0, ne, trueV, falseV) -> (select_cc X, Y, lt, trueV, falseV)
2021-03-07 09:44:56 -08:00
uadd_sat.ll
[RISCV] Fold (select_cc (setlt X, Y), 0, ne, trueV, falseV) -> (select_cc X, Y, lt, trueV, falseV)
2021-03-07 09:44:56 -08:00
umulo-128-legalisation-lowering.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
urem-lkk.ll
[TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on illegal types before type legalization if we can find a larger legal type that supports MUL.
2021-02-11 09:43:13 -08:00
urem-vector-lkk.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
usub_sat_plus.ll
[RISCV] Fold (select_cc (setlt X, Y), 0, ne, trueV, falseV) -> (select_cc X, Y, lt, trueV, falseV)
2021-03-07 09:44:56 -08:00
usub_sat.ll
[SelectionDAG] Add computeKnownBits support for ISD::USUBSAT.
2021-03-07 09:48:42 -08:00
vararg.ll
[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
2021-01-15 11:14:14 -08:00
vec3-setcc-crash.ll
[RISCV] Fix a codegen crash in getSetCCResultType
2021-01-27 10:22:54 +00:00
verify-instr.mir
…
wide-mem.ll
[RISCV] Fold ADDIs into load/stores with nonzero offsets
2020-07-06 17:32:57 +01:00
xaluo.ll
[RISCV] Fold (select_cc (setlt X, Y), 0, ne, trueV, falseV) -> (select_cc X, Y, lt, trueV, falseV)
2021-03-07 09:44:56 -08:00
zext-with-load-is-free.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
zfh-imm.ll
[RISCV] Support Zfh half-precision floating-point extension.
2020-12-03 09:16:33 +08:00