a781a706b9
These instructions previously used prefixes like v8x16 to signify that they were agnostic between float and int interpretations. We renamed these instructions to remove this form of prefix in https://github.com/WebAssembly/simd/issues/297 and https://github.com/WebAssembly/simd/issues/316 and this commit brings the names in LLVM up to date. Differential Revision: https://reviews.llvm.org/D93722
104 lines
4.4 KiB
LLVM
104 lines
4.4 KiB
LLVM
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
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; Test that SIMD shifts can be lowered correctly even with shift
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; values that are more complex than plain splats.
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target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
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target triple = "wasm32-unknown-unknown"
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;; TODO: Optimize this further by scalarizing the add
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; CHECK-LABEL: shl_add:
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; CHECK-NEXT: .functype shl_add (v128, i32, i32) -> (v128)
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; CHECK-NEXT: i8x16.splat $push1=, $1
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; CHECK-NEXT: i8x16.splat $push0=, $2
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; CHECK-NEXT: i8x16.add $push2=, $pop1, $pop0
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; CHECK-NEXT: i8x16.extract_lane_u $push3=, $pop2, 0
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; CHECK-NEXT: i8x16.shl $push4=, $0, $pop3
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; CHECK-NEXT: return $pop4
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define <16 x i8> @shl_add(<16 x i8> %v, i8 %a, i8 %b) {
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%t1 = insertelement <16 x i8> undef, i8 %a, i32 0
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%va = shufflevector <16 x i8> %t1, <16 x i8> undef, <16 x i32> zeroinitializer
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%t2 = insertelement <16 x i8> undef, i8 %b, i32 0
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%vb = shufflevector <16 x i8> %t2, <16 x i8> undef, <16 x i32> zeroinitializer
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%shift = add <16 x i8> %va, %vb
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%r = shl <16 x i8> %v, %shift
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ret <16 x i8> %r
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}
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; CHECK-LABEL: shl_abs:
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; CHECK-NEXT: .functype shl_abs (v128, i32) -> (v128)
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; CHECK-NEXT: i8x16.extract_lane_u $push8=, $0, 0
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; CHECK-NEXT: i8x16.splat $push0=, $1
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; CHECK-NEXT: i8x16.abs $push98=, $pop0
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; CHECK-NEXT: local.tee $push97=, $2=, $pop98
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; CHECK-NEXT: i8x16.extract_lane_u $push6=, $pop97, 0
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; CHECK-NEXT: i32.const $push2=, 7
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; CHECK-NEXT: i32.and $push7=, $pop6, $pop2
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; CHECK-NEXT: i32.shl $push9=, $pop8, $pop7
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; CHECK-NEXT: i8x16.splat $push10=, $pop9
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; CHECK-NEXT: i8x16.extract_lane_u $push4=, $0, 1
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; CHECK-NEXT: i8x16.extract_lane_u $push1=, $2, 1
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; CHECK-NEXT: i32.const $push96=, 7
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; CHECK-NEXT: i32.and $push3=, $pop1, $pop96
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; CHECK-NEXT: i32.shl $push5=, $pop4, $pop3
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; CHECK-NEXT: i8x16.replace_lane $push11=, $pop10, 1, $pop5
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; ...
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; CHECK: i8x16.extract_lane_u $push79=, $0, 15
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; CHECK-NEXT: i8x16.extract_lane_u $push77=, $2, 15
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; CHECK-NEXT: i32.const $push82=, 7
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; CHECK-NEXT: i32.and $push78=, $pop77, $pop82
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; CHECK-NEXT: i32.shl $push80=, $pop79, $pop78
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; CHECK-NEXT: i8x16.replace_lane $push81=, $pop76, 15, $pop80
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; CHECK-NEXT: return $pop81
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define <16 x i8> @shl_abs(<16 x i8> %v, i8 %a) {
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%t1 = insertelement <16 x i8> undef, i8 %a, i32 0
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%va = shufflevector <16 x i8> %t1, <16 x i8> undef, <16 x i32> zeroinitializer
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%nva = sub <16 x i8> zeroinitializer, %va
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%c = icmp sgt <16 x i8> %va, zeroinitializer
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%shift = select <16 x i1> %c, <16 x i8> %va, <16 x i8> %nva
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%r = shl <16 x i8> %v, %shift
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ret <16 x i8> %r
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}
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; CHECK-LABEL: shl_abs_add:
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; CHECK-NEXT: .functype shl_abs_add (v128, i32, i32) -> (v128)
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; CHECK-NEXT: i8x16.extract_lane_u $push11=, $0, 0
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; CHECK-NEXT: i8x16.splat $push1=, $1
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; CHECK-NEXT: i8x16.splat $push0=, $2
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; CHECK-NEXT: i8x16.add $push2=, $pop1, $pop0
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; CHECK-NEXT: i8x16.shuffle $push3=, $pop2, $0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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; CHECK-NEXT: i8x16.abs $push101=, $pop3
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; CHECK-NEXT: local.tee $push100=, $3=, $pop101
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; CHECK-NEXT: i8x16.extract_lane_u $push9=, $pop100, 0
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; CHECK-NEXT: i32.const $push5=, 7
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; CHECK-NEXT: i32.and $push10=, $pop9, $pop5
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; CHECK-NEXT: i32.shl $push12=, $pop11, $pop10
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; CHECK-NEXT: i8x16.splat $push13=, $pop12
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; CHECK-NEXT: i8x16.extract_lane_u $push7=, $0, 1
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; CHECK-NEXT: i8x16.extract_lane_u $push4=, $3, 1
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; CHECK-NEXT: i32.const $push99=, 7
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; CHECK-NEXT: i32.and $push6=, $pop4, $pop99
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; CHECK-NEXT: i32.shl $push8=, $pop7, $pop6
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; CHECK-NEXT: i8x16.replace_lane $push14=, $pop13, 1, $pop8
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; ...
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; CHECK: i8x16.extract_lane_u $push82=, $0, 15
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; CHECK-NEXT: i8x16.extract_lane_u $push80=, $3, 15
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; CHECK-NEXT: i32.const $push85=, 7
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; CHECK-NEXT: i32.and $push81=, $pop80, $pop85
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; CHECK-NEXT: i32.shl $push83=, $pop82, $pop81
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; CHECK-NEXT: i8x16.replace_lane $push84=, $pop79, 15, $pop83
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; CHECK-NEXT: return $pop84
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define <16 x i8> @shl_abs_add(<16 x i8> %v, i8 %a, i8 %b) {
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%t1 = insertelement <16 x i8> undef, i8 %a, i32 0
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%va = shufflevector <16 x i8> %t1, <16 x i8> undef, <16 x i32> zeroinitializer
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%t2 = insertelement <16 x i8> undef, i8 %b, i32 0
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%vb = shufflevector <16 x i8> %t2, <16 x i8> undef, <16 x i32> zeroinitializer
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%vadd = add <16 x i8> %va, %vb
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%nvadd = sub <16 x i8> zeroinitializer, %vadd
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%c = icmp sgt <16 x i8> %vadd, zeroinitializer
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%shift = select <16 x i1> %c, <16 x i8> %vadd, <16 x i8> %nvadd
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%r = shl <16 x i8> %v, %shift
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ret <16 x i8> %r
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}
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