e0919b189b
RegAllocGreedy uses SlotIndexes::getApproxInstrDistance to approximate the length of a live range for its heuristics. Renumbering all slot indexes with the default instruction distance ensures that this estimate will be as accurate as possible, and will not depend on the history of how instructions have been added to and removed from SlotIndexes's maps. This also means that enabling -early-live-intervals, which runs the SlotIndexes analysis earlier, will not cause large amounts of churn due to different register allocator decisions.
78 lines
3.4 KiB
LLVM
78 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -o - %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs | FileCheck %s
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@global = external protected addrspace(4) externally_initialized global [4096 x i64], align 16
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define hidden fastcc void @bar(i32 %arg, ptr %arg1, ptr %arg2, ptr %arg3, ptr %arg4, ptr %arg5, ptr %arg6) unnamed_addr align 2 {
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; CHECK-LABEL: bar:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v15, v12
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; CHECK-NEXT: v_mov_b32_e32 v14, v11
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; CHECK-NEXT: v_mov_b32_e32 v13, v10
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; CHECK-NEXT: v_mov_b32_e32 v12, v9
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; CHECK-NEXT: v_mov_b32_e32 v11, v8
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; CHECK-NEXT: v_mov_b32_e32 v10, v7
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; CHECK-NEXT: v_mov_b32_e32 v9, v6
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; CHECK-NEXT: v_mov_b32_e32 v8, v5
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; CHECK-NEXT: v_mov_b32_e32 v7, v4
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; CHECK-NEXT: v_mov_b32_e32 v6, v3
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; CHECK-NEXT: s_branch .LBB0_3
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; CHECK-NEXT: ; %bb.1: ; %LeafBlock
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; CHECK-NEXT: s_cbranch_scc1 .LBB0_5
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; CHECK-NEXT: ; %bb.2: ; %bb7
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; CHECK-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
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; CHECK-NEXT: s_getpc_b64 s[18:19]
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; CHECK-NEXT: s_add_u32 s18, s18, global@rel32@lo+1948
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; CHECK-NEXT: s_addc_u32 s19, s19, global@rel32@hi+1956
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; CHECK-NEXT: v_mov_b32_e32 v5, 0
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; CHECK-NEXT: v_mov_b32_e32 v0, s18
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; CHECK-NEXT: v_mov_b32_e32 v1, s19
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; CHECK-NEXT: s_getpc_b64 s[16:17]
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; CHECK-NEXT: s_add_u32 s16, s16, eggs@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s17, s17, eggs@rel32@hi+12
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; CHECK-NEXT: s_setpc_b64 s[16:17]
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; CHECK-NEXT: .LBB0_3: ; %LeafBlock1
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; CHECK-NEXT: s_cbranch_scc0 .LBB0_5
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; CHECK-NEXT: ; %bb.4: ; %bb8
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; CHECK-NEXT: v_mov_b32_e32 v0, v1
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; CHECK-NEXT: v_mov_b32_e32 v1, v2
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; CHECK-NEXT: v_mov_b32_e32 v2, v6
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; CHECK-NEXT: v_mov_b32_e32 v3, v7
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; CHECK-NEXT: v_mov_b32_e32 v4, v8
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; CHECK-NEXT: v_mov_b32_e32 v5, v9
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; CHECK-NEXT: v_mov_b32_e32 v6, v10
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; CHECK-NEXT: v_mov_b32_e32 v7, v11
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; CHECK-NEXT: v_mov_b32_e32 v8, v12
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; CHECK-NEXT: v_mov_b32_e32 v9, v13
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; CHECK-NEXT: v_mov_b32_e32 v10, v14
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; CHECK-NEXT: v_mov_b32_e32 v11, v15
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; CHECK-NEXT: s_getpc_b64 s[16:17]
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; CHECK-NEXT: s_add_u32 s16, s16, quux@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s17, s17, quux@rel32@hi+12
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; CHECK-NEXT: s_setpc_b64 s[16:17]
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; CHECK-NEXT: .LBB0_5: ; %bb9
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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bb:
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switch i32 undef, label %bb9 [
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i32 3, label %bb8
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i32 1, label %bb7
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]
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bb7: ; preds = %bb
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%tmp = load ptr, ptr undef, align 8
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tail call fastcc void @eggs(ptr noundef addrspacecast (ptr addrspace(4) getelementptr inbounds ([4096 x i64], ptr addrspace(4) @global, i64 0, i64 243) to ptr), ptr %tmp, ptr undef, ptr noundef nonnull align 8 dereferenceable(24) %arg2, ptr noundef %arg3, ptr noundef %arg4, ptr noundef %arg5)
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br label %bb9
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bb8: ; preds = %bb
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tail call fastcc void @quux(ptr noundef nonnull align 8 dereferenceable(24) %arg1, ptr noundef nonnull align 8 dereferenceable(24) %arg2, ptr noundef %arg3, ptr noundef %arg4, ptr noundef %arg5, ptr noundef nonnull align 8 dereferenceable(8) %arg6)
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br label %bb9
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bb9: ; preds = %bb8, %bb7, %bb
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ret void
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}
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declare dso_local fastcc void @eggs(ptr, ptr, ptr, ptr, ptr, ptr, ptr) unnamed_addr align 2
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declare dso_local fastcc void @quux(ptr, ptr, ptr, ptr, ptr, ptr) unnamed_addr align 2
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