70333de6cf
This change consolidates and cleans up various NVPTXISD target-specific nodes in order to simplify SDAG ISel. While there are some whitespace changes in the emitted PTX it is otherwise a non-functional change. NVPTXISD::Wrapper - This node was used to wrap external-symbol and global-address nodes. It is redundant and has been removed. Instead we use the non-target versions of these nodes and convert them appropriately during ISel. NVPTXISD::CALL - Much of the family of nodes used to represent a PTX call instruction have been replaced by this new single node. It corresponds to a single instruction and is therefore much simpler to create and lower.
131 lines
4.5 KiB
C++
131 lines
4.5 KiB
C++
//===-- NVPTXISelDAGToDAG.h - A dag to dag inst selector for NVPTX --------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the NVPTX target.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXISELDAGTODAG_H
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#define LLVM_LIB_TARGET_NVPTX_NVPTXISELDAGTODAG_H
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#include "MCTargetDesc/NVPTXBaseInfo.h"
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#include "NVPTX.h"
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#include "NVPTXISelLowering.h"
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#include "NVPTXRegisterInfo.h"
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#include "NVPTXTargetMachine.h"
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#include "llvm/ADT/MapVector.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/Support/Compiler.h"
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namespace llvm {
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struct NVPTXScopes {
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NVPTXScopes() = default;
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NVPTXScopes(LLVMContext &C);
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NVPTX::Scope operator[](SyncScope::ID ID) const;
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bool empty() const;
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private:
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SmallMapVector<SyncScope::ID, NVPTX::Scope, 8> Scopes{};
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};
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class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
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const NVPTXTargetMachine &TM;
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// If true, generate mul.wide from sext and mul
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bool doMulWide;
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NVPTX::DivPrecisionLevel getDivF32Level(const SDNode *N) const;
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bool usePrecSqrtF32(const SDNode *N) const;
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bool useF32FTZ() const;
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bool allowFMA() const;
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bool allowUnsafeFPMath() const;
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bool doRsqrtOpt() const;
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NVPTXScopes Scopes{};
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public:
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NVPTXDAGToDAGISel() = delete;
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explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm, CodeGenOptLevel OptLevel);
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bool runOnMachineFunction(MachineFunction &MF) override;
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const NVPTXSubtarget *Subtarget = nullptr;
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bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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InlineAsm::ConstraintCode ConstraintID,
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std::vector<SDValue> &OutOps) override;
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private:
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// Include the pieces autogenerated from the target description.
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#include "NVPTXGenDAGISel.inc"
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void Select(SDNode *N) override;
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bool tryIntrinsicChain(SDNode *N);
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bool tryIntrinsicVoid(SDNode *N);
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void SelectTexSurfHandle(SDNode *N);
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bool tryLoad(SDNode *N);
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bool tryLoadVector(SDNode *N);
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bool tryLDU(SDNode *N);
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bool tryLDG(MemSDNode *N);
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bool tryStore(SDNode *N);
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bool tryStoreVector(SDNode *N);
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bool tryLoadParam(SDNode *N);
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bool tryStoreRetval(SDNode *N);
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bool tryStoreParam(SDNode *N);
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bool tryFence(SDNode *N);
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void SelectAddrSpaceCast(SDNode *N);
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bool tryBFE(SDNode *N);
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bool tryBF16ArithToFMA(SDNode *N);
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bool tryConstantFP(SDNode *N);
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bool SelectSETP_F16X2(SDNode *N);
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bool SelectSETP_BF16X2(SDNode *N);
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bool tryUNPACK_VECTOR(SDNode *N);
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bool tryEXTRACT_VECTOR_ELEMENT(SDNode *N);
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void SelectV2I64toI128(SDNode *N);
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void SelectI128toV2I64(SDNode *N);
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void SelectCpAsyncBulkTensorG2SCommon(SDNode *N, bool IsIm2Col = false);
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void SelectCpAsyncBulkTensorS2GCommon(SDNode *N, bool IsIm2Col = false);
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void SelectCpAsyncBulkTensorPrefetchCommon(SDNode *N, bool IsIm2Col = false);
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void SelectCpAsyncBulkTensorReduceCommon(SDNode *N, unsigned RedOp,
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bool IsIm2Col = false);
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void SelectTcgen05Ld(SDNode *N, bool hasOffset = false);
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void SelectTcgen05St(SDNode *N, bool hasOffset = false);
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inline SDValue getI32Imm(unsigned Imm, const SDLoc &DL) {
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return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
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}
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bool SelectADDR(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool ChkMemSDNodeAddressSpace(SDNode *N, unsigned int spN) const;
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static unsigned GetConvertOpcode(MVT DestTy, MVT SrcTy, LoadSDNode *N);
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// Returns the Memory Order and Scope that the PTX memory instruction should
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// use, and inserts appropriate fence instruction before the memory
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// instruction, if needed to implement the instructions memory order. Required
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// fences after the instruction need to be handled elsewhere.
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std::pair<NVPTX::Ordering, NVPTX::Scope>
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insertMemoryInstructionFence(SDLoc DL, SDValue &Chain, MemSDNode *N);
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NVPTX::Scope getOperationScope(MemSDNode *N, NVPTX::Ordering O) const;
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};
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class NVPTXDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
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public:
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static char ID;
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explicit NVPTXDAGToDAGISelLegacy(NVPTXTargetMachine &tm,
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CodeGenOptLevel OptLevel);
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};
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} // end namespace llvm
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#endif
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