clang-p2996

AsmParser

Remove an unused function.

2018-02-16 22:46:47 +00:00

Disassembler

[AMDGPU][MC] Corrected dst/data size for MIMG opcodes with d16 modifier

2018-02-05 14:18:53 +00:00

InstPrinter

[AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32

2018-01-15 18:49:15 +00:00

MCTargetDesc

AMDGPU: Remove unused private member of AMDGPUTargetELFStreamer

2018-02-16 23:04:11 +00:00

TargetInfo

Add backend name to Target to enable runtime info to be fed back into TableGen

2017-11-15 23:55:44 +00:00

Utils

AMDGPU: Bring processors and features in sync with the spec

2018-02-16 21:26:25 +00:00

AMDGPU.h

[AMDGPU] Change constant addr space to 4

2018-02-13 18:00:25 +00:00

AMDGPU.td

AMDGPU: Bring processors and features in sync with the spec

2018-02-16 21:26:25 +00:00

AMDGPUAliasAnalysis.cpp

[AMDGPU] Change constant addr space to 4

2018-02-13 18:00:25 +00:00

AMDGPUAliasAnalysis.h

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AMDGPUAlwaysInlinePass.cpp

AMDGPU: Add option to stress calls

2017-09-21 07:00:48 +00:00

AMDGPUAnnotateKernelFeatures.cpp

[Analysis] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes. Also affected in files (NFC).

2017-08-31 21:56:16 +00:00

AMDGPUAnnotateUniformValues.cpp

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AMDGPUArgumentUsageInfo.cpp

[CodeGen] Rename functions PrintReg* to printReg*

2017-11-28 12:42:37 +00:00

AMDGPUArgumentUsageInfo.h

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AMDGPUAsmPrinter.cpp

[AMDGPU] do not generate .AMDGPU.config for amdpal os type

2018-02-06 13:39:38 +00:00

AMDGPUAsmPrinter.h

[AMDGPU] add labels to +DumpCode output

2017-12-08 14:09:34 +00:00

AMDGPUCallingConv.td

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AMDGPUCallLowering.cpp

[AMDGPU] Change constant addr space to 4

2018-02-13 18:00:25 +00:00

AMDGPUCallLowering.h

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AMDGPUCodeGenPrepare.cpp

Reapply "AMDGPU: Add 32-bit constant address space"

2018-02-09 16:57:57 +00:00

AMDGPUFrameLowering.cpp

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AMDGPUFrameLowering.h

Move TargetFrameLowering.h to CodeGen where it's implemented

2017-11-03 22:32:11 +00:00

AMDGPUGenRegisterBankInfo.def

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AMDGPUInline.cpp

[AMDGPU] Port of HSAIL inliner

2017-09-20 04:25:58 +00:00

AMDGPUInstrInfo.cpp

Reapply "AMDGPU: Add 32-bit constant address space"

2018-02-09 16:57:57 +00:00

AMDGPUInstrInfo.h

AMDGPU: Fix layering issue

2018-02-09 16:57:48 +00:00

AMDGPUInstrInfo.td

AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}

2018-01-31 20:18:04 +00:00

AMDGPUInstructions.td

AMDGPU: Select BFI patterns with 64-bit ints

2018-02-07 00:21:34 +00:00

AMDGPUInstructionSelector.cpp

Reapply "AMDGPU: Add 32-bit constant address space"

2018-02-09 16:57:57 +00:00

AMDGPUInstructionSelector.h

[globalisel][tablegen] Generate rule coverage and use it to identify untested rules

2017-11-16 00:46:35 +00:00

AMDGPUIntrinsicInfo.cpp

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AMDGPUIntrinsicInfo.h

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AMDGPUIntrinsics.td

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AMDGPUISelDAGToDAG.cpp

Reapply "AMDGPU: Add 32-bit constant address space"

2018-02-09 16:57:57 +00:00

AMDGPUISelLowering.cpp

AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}

2018-01-31 20:18:04 +00:00

AMDGPUISelLowering.h

AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}

2018-01-31 20:18:04 +00:00

AMDGPULegalizerInfo.cpp

[AMDGPU] Change constant addr space to 4

2018-02-13 18:00:25 +00:00

AMDGPULegalizerInfo.h

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AMDGPULibCalls.cpp

Make helpers static. NFC.

2017-11-24 14:55:41 +00:00

AMDGPULibFunc.cpp

[AMDGPU] Remove hardcoded address space value from AMDGPULibFunc

2017-11-04 17:37:43 +00:00

AMDGPULibFunc.h

[AMDGPU] Remove hardcoded address space value from AMDGPULibFunc

2017-11-04 17:37:43 +00:00

AMDGPULowerIntrinsics.cpp

…

AMDGPUMachineCFGStructurizer.cpp

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

2017-12-07 10:40:31 +00:00

AMDGPUMachineFunction.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

AMDGPUMachineFunction.h

…

AMDGPUMachineModuleInfo.cpp

…

AMDGPUMachineModuleInfo.h

AMDGPU: Handle more than one memory operand in SIMemoryLegalizer

2017-09-07 16:14:21 +00:00

AMDGPUMacroFusion.cpp

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AMDGPUMacroFusion.h

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AMDGPUMCInstLower.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

AMDGPUMCInstLower.h

…

AMDGPUOpenCLEnqueuedBlockLowering.cpp

AMDGPU: Fix set but not used warnings related to AMDGPUAS

2017-11-01 19:12:38 +00:00

AMDGPUOpenCLImageTypeLoweringPass.cpp

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AMDGPUPromoteAlloca.cpp

AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements

2018-02-16 19:14:17 +00:00

AMDGPUPTNote.h

AMDGPU/NFC: Move AMDGPU specific note types to ELF.h

2017-10-12 18:59:54 +00:00

AMDGPURegAsmNames.inc.cpp

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AMDGPURegisterBankInfo.cpp

AMDGPU: Fix layering issue

2018-02-09 16:57:48 +00:00

AMDGPURegisterBankInfo.h

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AMDGPURegisterBanks.td

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AMDGPURegisterInfo.cpp

[AMDGPU] Make sure all super regs of reserved regs are marked reserved.

2018-01-24 18:09:53 +00:00

AMDGPURegisterInfo.h

[AMDGPU] Return true in enableMultipleCopyHints().

2018-02-17 10:00:28 +00:00

AMDGPURegisterInfo.td

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AMDGPURewriteOutArguments.cpp

…

AMDGPUSubtarget.cpp

[AMDGPU][MC] Added validation of d16 and r128 modifiers of MIMG opcodes

2018-02-05 12:45:43 +00:00

AMDGPUSubtarget.h

AMDGPU: Bring processors and features in sync with the spec

2018-02-16 21:26:25 +00:00

AMDGPUTargetMachine.cpp

[AMDGPU] Change constant addr space to 4

2018-02-13 18:00:25 +00:00

AMDGPUTargetMachine.h

(Re-landing) Expose a TargetMachine::getTargetTransformInfo function

2017-12-22 18:21:59 +00:00

AMDGPUTargetObjectFile.cpp

AMDGPU: Fix set but not used warnings related to AMDGPUAS

2017-11-01 19:12:38 +00:00

AMDGPUTargetObjectFile.h

…

AMDGPUTargetTransformInfo.cpp

[AMDGPU] Increased vector length for global/constant loads.

2018-02-19 16:42:49 +00:00

AMDGPUTargetTransformInfo.h

[AMDGPU] Increased vector length for global/constant loads.

2018-02-19 16:42:49 +00:00

AMDGPUUnifyDivergentExitNodes.cpp

[Transforms] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).

2017-10-17 21:27:42 +00:00

AMDGPUUnifyMetadata.cpp

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AMDILCFGStructurizer.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

AMDKernelCodeT.h

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BUFInstructions.td

AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the target has UnpackedD16VMem feature.

2018-02-01 18:41:33 +00:00

CaymanInstructions.td

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

2017-12-07 10:40:31 +00:00

CMakeLists.txt

AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)

2017-11-20 14:35:53 +00:00

DSInstructions.td

[AMDGPU] add LDS f32 intrinsics

2018-01-17 14:05:05 +00:00

EvergreenInstructions.td

AMDGPU: Select BFI patterns with 64-bit ints

2018-02-07 00:21:34 +00:00

FLATInstructions.td

[AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodes

2017-11-27 17:14:35 +00:00

GCNHazardRecognizer.cpp

[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards().

2017-12-07 20:34:25 +00:00

GCNHazardRecognizer.h

[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards().

2017-12-07 20:34:25 +00:00

GCNILPSched.cpp

AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)

2017-11-20 14:35:53 +00:00

GCNIterativeScheduler.cpp

[NFC] fix trivial typos in comments and documents

2018-01-29 05:17:03 +00:00

GCNIterativeScheduler.h

AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)

2017-11-20 14:35:53 +00:00

GCNMinRegStrategy.cpp

…

GCNProcessors.td

AMDGPU: Bring processors and features in sync with the spec

2018-02-16 21:26:25 +00:00

GCNRegPressure.cpp

Rename LiveIntervalAnalysis.h to LiveIntervals.h

2017-12-13 02:51:04 +00:00

GCNRegPressure.h

Rename LiveIntervalAnalysis.h to LiveIntervals.h

2017-12-13 02:51:04 +00:00

GCNSchedStrategy.cpp

[NFC] fix trivial typos in comments

2018-01-22 05:54:46 +00:00

GCNSchedStrategy.h

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LLVMBuild.txt

…

MIMGInstructions.td

[AMDGPU][MC] Added support of 64-bit image atomics

2018-01-26 15:43:29 +00:00

R600ClauseMergePass.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

R600ControlFlowFinalizer.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

R600Defines.h

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R600EmitClauseMarkers.cpp

…

R600ExpandSpecialInstrs.cpp

…

R600FrameLowering.cpp

…

R600FrameLowering.h

…

R600InstrFormats.td

AMDGPU: Remove global isGCN predicates

2017-10-03 00:06:41 +00:00

R600InstrInfo.cpp

[AMDGPU] Make sure all super regs of reserved regs are marked reserved.

2018-01-24 18:09:53 +00:00

R600InstrInfo.h

[AMDGPU] Make sure all super regs of reserved regs are marked reserved.

2018-01-24 18:09:53 +00:00

R600Instructions.td

AMDGPU: Move ADDRIndirect complex pattern into R600Instructions.td

2018-01-29 23:29:26 +00:00

R600Intrinsics.td

…

R600ISelLowering.cpp

AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction

2017-12-04 23:07:28 +00:00

R600ISelLowering.h

…

R600MachineFunctionInfo.cpp

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R600MachineFunctionInfo.h

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R600MachineScheduler.cpp

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R600MachineScheduler.h

…

R600OptimizeVectorRegisters.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

R600Packetizer.cpp

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R600Processors.td

AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction

2017-12-04 23:07:28 +00:00

R600RegisterInfo.cpp

[AMDGPU] Make sure all super regs of reserved regs are marked reserved.

2018-01-24 18:09:53 +00:00

R600RegisterInfo.h

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R600RegisterInfo.td

…

R600Schedule.td

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R700Instructions.td

…

SIAnnotateControlFlow.cpp

AMDGPU: Error in SIAnnotateControlFlow instead of assert

2018-01-17 16:30:01 +00:00

SIDebuggerInsertNops.cpp

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SIDefines.h

AMDGPU/SI: Add d16 support for image intrinsics.

2018-01-18 22:08:53 +00:00

SIFixSGPRCopies.cpp

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

SIFixVGPRCopies.cpp

…

SIFixWWMLiveness.cpp

Rename LiveIntervalAnalysis.h to LiveIntervals.h

2017-12-13 02:51:04 +00:00

SIFoldOperands.cpp

AMDGPU: Don't crash when trying to fold implicit operands

2018-02-08 01:12:46 +00:00

SIFrameLowering.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

SIFrameLowering.h

[AMDGPU] AMDPAL scratch buffer support

2017-09-29 09:49:35 +00:00

SIInsertSkips.cpp

[AMDGPU] isRenamable fixes to support copy forwarding

2018-01-30 17:37:39 +00:00

SIInsertWaitcnts.cpp

[AMDGPU] Make note of existing waitcnt instrs; this is add-on work related to suppression of redundant waitcnt instrs. It is necessary to make note of these existing waitcnt instrs so that we do not fall into an infinite loop when handling loops. Also, [NFC] some minor code clean-up.

2018-02-19 19:19:59 +00:00

SIInsertWaits.cpp

[NFC] fix trivial typos in comments and documents

2018-01-29 05:17:03 +00:00

SIInstrFormats.td

[AMDGPU] isRenamable fixes to support copy forwarding

2018-01-30 17:37:39 +00:00

SIInstrInfo.cpp

AMDGPU: Fix S_BUFFER_LOAD_DWORD_SGPR moveToVALU

2018-02-06 15:17:55 +00:00

SIInstrInfo.h

[NFC] fix trivial typos in comments

2018-01-24 05:04:35 +00:00

SIInstrInfo.td

[AMDGPU][MC] Corrected parsing of image opcode modifiers r128 and d16

2018-01-29 14:20:42 +00:00

SIInstructions.td

AMDGPU: Remove tied operand from si_else

2018-02-09 17:18:38 +00:00

SIIntrinsics.td

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SIISelLowering.cpp

AMDGPU/SI: Turn off GPR Indexing Mode immediately after the interested instruction.

2018-02-16 16:31:30 +00:00

SIISelLowering.h

AMDGPU/SI: Add d16 support for buffer intrinsics.

2018-01-12 21:12:19 +00:00

SILoadStoreOptimizer.cpp

AMDGPU: Fix incorrect reordering when inline asm defines LDS address

2018-02-08 01:56:14 +00:00

SILowerControlFlow.cpp

Rename LiveIntervalAnalysis.h to LiveIntervals.h

2017-12-13 02:51:04 +00:00

SILowerI1Copies.cpp

Rename LiveIntervalAnalysis.h to LiveIntervals.h

2017-12-13 02:51:04 +00:00

SIMachineFunctionInfo.cpp

Reapply "AMDGPU: Add 32-bit constant address space"

2018-02-09 16:57:57 +00:00

SIMachineFunctionInfo.h

Reapply "AMDGPU: Add 32-bit constant address space"

2018-02-09 16:57:57 +00:00

SIMachineScheduler.cpp

Rename LiveIntervalAnalysis.h to LiveIntervals.h

2017-12-13 02:51:04 +00:00

SIMachineScheduler.h

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SIMemoryLegalizer.cpp

[AMDGPU] More descriptive names in the memory legalizer

2018-02-09 06:05:33 +00:00

SIOptimizeExecMasking.cpp

[AMDGPU][X86][Mips] Make sure renamable bit not set for reserved regs

2018-01-29 18:47:48 +00:00

SIOptimizeExecMaskingPreRA.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

SIPeepholeSDWA.cpp

AMDGPU: Process SDWA block at a time

2018-02-08 22:46:41 +00:00

SIRegisterInfo.cpp

[AMDGPU] Make sure all super regs of reserved regs are marked reserved.

2018-01-24 18:09:53 +00:00

SIRegisterInfo.h

[AMDGPU] Make sure all super regs of reserved regs are marked reserved.

2018-01-24 18:09:53 +00:00

SIRegisterInfo.td

[AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support

2018-01-10 14:22:19 +00:00

SISchedule.td

…

SIShrinkInstructions.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

SIWholeQuadMode.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

SMInstructions.td

Reapply "AMDGPU: Add 32-bit constant address space"

2018-02-09 16:57:57 +00:00

SOPInstructions.td

AMDGPU: Add llvm.amdgcn.wqm.vote intrinsic

2017-10-24 10:26:59 +00:00

VIInstrFormats.td

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VIInstructions.td

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VOP1Instructions.td

[AMDGPU] Copy impdefs from pseudo to real instructions

2018-01-15 17:55:35 +00:00

VOP2Instructions.td

AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}

2018-01-31 20:18:04 +00:00

VOP3Instructions.td

[AMDGPU] isRenamable fixes to support copy forwarding

2018-01-30 17:37:39 +00:00

VOP3PInstructions.td

AMDGPU: Add max-mix-insts subtarget feature

2017-10-25 07:00:51 +00:00

VOPCInstructions.td

[AMDGPU] Copy impdefs from pseudo to real instructions

2018-01-15 17:55:35 +00:00

VOPInstructions.td

[AMDGPU] isRenamable fixes to support copy forwarding

2018-01-30 17:37:39 +00:00