5f8f34e459
We've been running doxygen with the autobrief option for a couple of years now. This makes the \brief markers into our comments redundant. Since they are a visual distraction and we don't want to encourage more \brief markers in new code either, this patch removes them all. Patch produced by for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done Differential Revision: https://reviews.llvm.org/D46290 llvm-svn: 331272
89 lines
3.4 KiB
TableGen
89 lines
3.4 KiB
TableGen
//- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This is a target description file for the WebAssembly architecture,
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/// which is also known as "wasm".
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///
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// WebAssembly Subtarget features.
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//===----------------------------------------------------------------------===//
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def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "true",
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"Enable 128-bit SIMD">;
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def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true",
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"Enable Atomics">;
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def FeatureNontrappingFPToInt :
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SubtargetFeature<"nontrapping-fptoint",
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"HasNontrappingFPToInt", "true",
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"Enable non-trapping float-to-int conversion operators">;
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def FeatureSignExt :
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SubtargetFeature<"sign-ext",
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"HasSignExt", "true",
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"Enable sign extension operators">;
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def FeatureExceptionHandling :
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SubtargetFeature<"exception-handling", "HasExceptionHandling", "true",
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"Enable Wasm exception handling">;
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//===----------------------------------------------------------------------===//
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// Architectures.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "WebAssemblyRegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "WebAssemblyInstrInfo.td"
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def WebAssemblyInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// WebAssembly Processors supported.
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//===----------------------------------------------------------------------===//
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// Minimal Viable Product.
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def : ProcessorModel<"mvp", NoSchedModel, []>;
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// Generic processor: latest stable version.
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def : ProcessorModel<"generic", NoSchedModel, []>;
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// Latest and greatest experimental version of WebAssembly. Bugs included!
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def : ProcessorModel<"bleeding-edge", NoSchedModel,
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[FeatureSIMD128, FeatureAtomics]>;
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//===----------------------------------------------------------------------===//
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// Target Declaration
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//===----------------------------------------------------------------------===//
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def WebAssemblyAsmParser : AsmParser {
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// The physical register names are not in the binary format or asm text
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let ShouldEmitMatchRegisterName = 0;
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}
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def WebAssembly : Target {
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let InstructionSet = WebAssemblyInstrInfo;
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let AssemblyParsers = [WebAssemblyAsmParser];
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}
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