7717c0071d
This refactor patch means to remove CPU_SPECIFIC* MACROs in X86TargetParser.def and move those information into ProcInfo of X86TargetParser.cpp. Since these two files both maintain a table with redundant info such as cpuname and its features supported. CPU_SPECIFIC* MACROs define some different information. This patch dealt with them in these ways when moving: 1.mangling This is now moved to Mangling in ProcInfo and directly initialized at array of Processors. CPUs don't support cpu_dispatch/specific are assigned '\0' as mangling. 2.CPU alias The alias cpu will also be initialized in array of Processors, its attributes will be same as its alias target cpu. Same feature list, same mangling. 3.TUNE_NAME Before my change, some cpu names support cpu_dispatch/specific are not supported in X86.td, which means optimizer/backend doesn't recognize them. So they use a different TUNE_NAME to generate in IR. In this patch, I added these missing cpu support at X86.td by utilizing existing Features and XXXTunings, so that each cpu name can directly use its own name as TUNE_NAME to be supported by optimizer/backend. 4.Feature list The feature list of one CPU maintained in X86TargetParser.def is not same as the one in X86TargetParser.cpp. It only maintains part of features of one CPU (features defined by X86_FEATURE_COMPAT). While X86TargetParser.cpp maintains a complete one. This patch abandons the feature list maintained by CPU_SPECIFIC* MACROs because assigning a CPU with a complete one doesn't affect the functionality of cpu_dispatch/specific. Except these four info, since some of CPUs supported by cpu_dispatch/specific doesn's support clang options like -march, -mtune before, this patch also kept this behavior still by adding another member OnlyForCPUDispatchSpecific in ProcInfo. Reviewed By: pengfei, RKSimon Differential Revision: https://reviews.llvm.org/D151696
807 lines
38 KiB
C++
807 lines
38 KiB
C++
//===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise X86 hardware features.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/TargetParser/X86TargetParser.h"
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#include "llvm/ADT/StringSwitch.h"
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#include <numeric>
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using namespace llvm;
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using namespace llvm::X86;
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namespace {
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/// Container class for CPU features.
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/// This is a constexpr reimplementation of a subset of std::bitset. It would be
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/// nice to use std::bitset directly, but it doesn't support constant
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/// initialization.
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class FeatureBitset {
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static constexpr unsigned NUM_FEATURE_WORDS =
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(X86::CPU_FEATURE_MAX + 31) / 32;
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// This cannot be a std::array, operator[] is not constexpr until C++17.
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uint32_t Bits[NUM_FEATURE_WORDS] = {};
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public:
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constexpr FeatureBitset() = default;
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constexpr FeatureBitset(std::initializer_list<unsigned> Init) {
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for (auto I : Init)
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set(I);
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}
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bool any() const {
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return llvm::any_of(Bits, [](uint64_t V) { return V != 0; });
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}
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constexpr FeatureBitset &set(unsigned I) {
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// GCC <6.2 crashes if this is written in a single statement.
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uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32));
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Bits[I / 32] = NewBits;
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return *this;
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}
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constexpr bool operator[](unsigned I) const {
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uint32_t Mask = uint32_t(1) << (I % 32);
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return (Bits[I / 32] & Mask) != 0;
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}
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constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
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for (unsigned I = 0, E = std::size(Bits); I != E; ++I) {
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// GCC <6.2 crashes if this is written in a single statement.
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uint32_t NewBits = Bits[I] & RHS.Bits[I];
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Bits[I] = NewBits;
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}
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return *this;
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}
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constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
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for (unsigned I = 0, E = std::size(Bits); I != E; ++I) {
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// GCC <6.2 crashes if this is written in a single statement.
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uint32_t NewBits = Bits[I] | RHS.Bits[I];
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Bits[I] = NewBits;
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}
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return *this;
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}
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// gcc 5.3 miscompiles this if we try to write this using operator&=.
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constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
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FeatureBitset Result;
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for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
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Result.Bits[I] = Bits[I] & RHS.Bits[I];
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return Result;
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}
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// gcc 5.3 miscompiles this if we try to write this using operator&=.
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constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
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FeatureBitset Result;
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for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
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Result.Bits[I] = Bits[I] | RHS.Bits[I];
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return Result;
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}
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constexpr FeatureBitset operator~() const {
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FeatureBitset Result;
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for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
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Result.Bits[I] = ~Bits[I];
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return Result;
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}
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constexpr bool operator!=(const FeatureBitset &RHS) const {
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for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
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if (Bits[I] != RHS.Bits[I])
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return true;
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return false;
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}
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};
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struct ProcInfo {
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StringLiteral Name;
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X86::CPUKind Kind;
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unsigned KeyFeature;
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FeatureBitset Features;
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char Mangling;
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bool OnlyForCPUDispatchSpecific;
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};
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struct FeatureInfo {
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StringLiteral Name;
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FeatureBitset ImpliedFeatures;
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};
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} // end anonymous namespace
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#define X86_FEATURE(ENUM, STRING) \
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constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
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#include "llvm/TargetParser/X86TargetParser.def"
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// Pentium with MMX.
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constexpr FeatureBitset FeaturesPentiumMMX =
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FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
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// Pentium 2 and 3.
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constexpr FeatureBitset FeaturesPentium2 =
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FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR | FeatureCMOV;
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constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
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// Pentium 4 CPUs
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constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2;
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constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3;
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constexpr FeatureBitset FeaturesNocona =
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FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
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// Basic 64-bit capable CPU.
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constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
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constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF |
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FeaturePOPCNT | FeatureCRC32 |
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FeatureSSE4_2 | FeatureCMPXCHG16B;
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constexpr FeatureBitset FeaturesX86_64_V3 =
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FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
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FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
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constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 |
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FeatureAVX512BW | FeatureAVX512CD |
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FeatureAVX512DQ | FeatureAVX512VL;
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// Intel Core CPUs
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constexpr FeatureBitset FeaturesCore2 =
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FeaturesNocona | FeatureSAHF | FeatureSSSE3;
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constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
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constexpr FeatureBitset FeaturesNehalem =
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FeaturesPenryn | FeaturePOPCNT | FeatureCRC32 | FeatureSSE4_2;
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constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL;
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constexpr FeatureBitset FeaturesSandyBridge =
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FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
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constexpr FeatureBitset FeaturesIvyBridge =
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FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
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constexpr FeatureBitset FeaturesHaswell =
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FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
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FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
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constexpr FeatureBitset FeaturesBroadwell =
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FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
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// Intel Knights Landing and Knights Mill
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// Knights Landing has feature parity with Broadwell.
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constexpr FeatureBitset FeaturesKNL =
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FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD |
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FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
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constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
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// Intel Skylake processors.
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constexpr FeatureBitset FeaturesSkylakeClient =
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FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
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FeatureXSAVES | FeatureSGX;
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// SkylakeServer inherits all SkylakeClient features except SGX.
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// FIXME: That doesn't match gcc.
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constexpr FeatureBitset FeaturesSkylakeServer =
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(FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
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FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
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FeaturePKU;
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constexpr FeatureBitset FeaturesCascadeLake =
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FeaturesSkylakeServer | FeatureAVX512VNNI;
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constexpr FeatureBitset FeaturesCooperLake =
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FeaturesCascadeLake | FeatureAVX512BF16;
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// Intel 10nm processors.
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constexpr FeatureBitset FeaturesCannonlake =
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FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
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FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
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FeaturePKU | FeatureSHA;
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constexpr FeatureBitset FeaturesICLClient =
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FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
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FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID |
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FeatureVAES | FeatureVPCLMULQDQ;
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constexpr FeatureBitset FeaturesRocketlake = FeaturesICLClient & ~FeatureSGX;
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constexpr FeatureBitset FeaturesICLServer =
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FeaturesICLClient | FeatureCLWB | FeaturePCONFIG | FeatureWBNOINVD;
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constexpr FeatureBitset FeaturesTigerlake =
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FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
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FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
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constexpr FeatureBitset FeaturesSapphireRapids =
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FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE |
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FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVXVNNI | FeatureCLDEMOTE |
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FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
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FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
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FeatureWAITPKG;
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constexpr FeatureBitset FeaturesGraniteRapids =
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FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI |
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FeatureAMX_COMPLEX;
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// Intel Atom processors.
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// Bonnell has feature parity with Core2 and adds MOVBE.
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constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
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// Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
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constexpr FeatureBitset FeaturesSilvermont =
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FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
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constexpr FeatureBitset FeaturesGoldmont =
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FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
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FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
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FeatureXSAVEOPT | FeatureXSAVES;
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constexpr FeatureBitset FeaturesGoldmontPlus =
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FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
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constexpr FeatureBitset FeaturesTremont =
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FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
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constexpr FeatureBitset FeaturesAlderlake =
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FeaturesTremont | FeatureADX | FeatureBMI | FeatureBMI2 | FeatureF16C |
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FeatureFMA | FeatureINVPCID | FeatureLZCNT | FeaturePCONFIG | FeaturePKU |
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FeatureSERIALIZE | FeatureSHSTK | FeatureVAES | FeatureVPCLMULQDQ |
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FeatureCLDEMOTE | FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG |
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FeatureAVXVNNI | FeatureHRESET | FeatureWIDEKL;
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constexpr FeatureBitset FeaturesSierraforest =
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FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA |
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FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
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constexpr FeatureBitset FeaturesGrandridge =
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FeaturesSierraforest | FeatureRAOINT;
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// Geode Processor.
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constexpr FeatureBitset FeaturesGeode =
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FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
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// K6 processor.
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constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
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// K7 and K8 architecture processors.
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constexpr FeatureBitset FeaturesAthlon =
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FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
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constexpr FeatureBitset FeaturesAthlonXP =
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FeaturesAthlon | FeatureFXSR | FeatureSSE;
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constexpr FeatureBitset FeaturesK8 =
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FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
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constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
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constexpr FeatureBitset FeaturesAMDFAM10 =
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FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
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FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
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// Bobcat architecture processors.
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constexpr FeatureBitset FeaturesBTVER1 =
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FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
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FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
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FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
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FeatureSAHF;
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constexpr FeatureBitset FeaturesBTVER2 =
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FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureCRC32 |
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FeatureF16C | FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
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// AMD Bulldozer architecture processors.
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constexpr FeatureBitset FeaturesBDVER1 =
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FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
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FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | FeatureFMA4 |
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FeatureFXSR | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL |
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FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 |
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FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A |
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FeatureXOP | FeatureXSAVE;
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constexpr FeatureBitset FeaturesBDVER2 =
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FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
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constexpr FeatureBitset FeaturesBDVER3 =
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FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
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constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
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FeatureBMI2 | FeatureMOVBE |
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FeatureMWAITX | FeatureRDRND;
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// AMD Zen architecture processors.
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constexpr FeatureBitset FeaturesZNVER1 =
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FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
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FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
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FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT |
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FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT |
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FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
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FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
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FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
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FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
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FeatureXSAVEOPT | FeatureXSAVES;
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constexpr FeatureBitset FeaturesZNVER2 = FeaturesZNVER1 | FeatureCLWB |
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FeatureRDPID | FeatureRDPRU |
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FeatureWBNOINVD;
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static constexpr FeatureBitset FeaturesZNVER3 = FeaturesZNVER2 |
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FeatureINVPCID | FeaturePKU |
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FeatureVAES | FeatureVPCLMULQDQ;
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static constexpr FeatureBitset FeaturesZNVER4 =
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FeaturesZNVER3 | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
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FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
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FeatureAVX512VBMI2 | FeatureAVX512VNNI | FeatureAVX512BITALG |
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FeatureAVX512VPOPCNTDQ | FeatureAVX512BF16 | FeatureGFNI |
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FeatureSHSTK;
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// D151696 tranplanted Mangling and OnlyForCPUDispatchSpecific from
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// X86TargetParser.def to here. They are assigned by following ways:
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// 1. Copy the mangling from the original CPU_SPEICIFC MACROs. If no, assign
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// to '\0' by default, which means not support cpu_specific/dispatch feature.
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// 2. set OnlyForCPUDispatchSpecific as true if this cpu name was not
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// listed here before, which means it doesn't support -march, -mtune and so on.
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// FIXME: Remove OnlyForCPUDispatchSpecific after all CPUs here support both
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// cpu_dispatch/specific() feature and -march, -mtune, and so on.
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constexpr ProcInfo Processors[] = {
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// Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
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{ {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B, '\0', false },
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{ {"generic"}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B | Feature64BIT, 'A', true },
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// i386-generation processors.
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{ {"i386"}, CK_i386, ~0U, FeatureX87, '\0', false },
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// i486-generation processors.
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{ {"i486"}, CK_i486, ~0U, FeatureX87, '\0', false },
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{ {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX, '\0', false },
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{ {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW, '\0', false },
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{ {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW, '\0', false },
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// i586-generation processors, P5 microarchitecture based.
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{ {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B, '\0', false },
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{ {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B, 'B', false },
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{ {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, '\0', false },
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{ {"pentium_mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, 'D', true },
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// i686-generation processors, P6 / Pentium M microarchitecture based.
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{ {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false },
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{ {"pentium_pro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', true },
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{ {"i686"}, CK_i686, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false },
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{ {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2, '\0', false },
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{ {"pentium_ii"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', true },
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{ {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3, '\0', false },
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{ {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3, '\0', false },
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{ {"pentium_iii"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
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{ {"pentium_iii_no_xmm_regs"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
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{ {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4, '\0', false },
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{ {"pentium_m"}, CK_PentiumM, ~0U, FeaturesPentium4, 'K', true },
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{ {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3, '\0', false },
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{ {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott, '\0', false },
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// Netburst microarchitecture based processors.
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{ {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4, '\0', false },
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{ {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4, '\0', false },
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{ {"pentium_4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', true },
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{ {"pentium_4_sse3"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', true },
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{ {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott, '\0', false },
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{ {"nocona"}, CK_Nocona, ~0U, FeaturesNocona, '\0', false },
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// Core microarchitecture based processors.
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{ {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2, '\0', false },
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{ {"core_2_duo_ssse3"}, CK_Core2, ~0U, FeaturesCore2, 'M', true },
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{ {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn, '\0', false },
|
|
{ {"core_2_duo_sse4_1"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', true },
|
|
// Atom processors
|
|
{ {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, '\0', false },
|
|
{ {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
|
|
{ {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, '\0', false },
|
|
{ {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, '\0', false },
|
|
{ {"atom_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'c', true },
|
|
{ {"atom_sse4_2_movbe"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'd', true },
|
|
{ {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'i', false },
|
|
{ {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', false },
|
|
{ {"goldmont_plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', true },
|
|
{ {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont, '\0', false },
|
|
// Nehalem microarchitecture based processors.
|
|
{ {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, '\0', false },
|
|
{ {"core_i7_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', true },
|
|
{ {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, '\0', false },
|
|
// Westmere microarchitecture based processors.
|
|
{ {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere, '\0', false },
|
|
{ {"core_aes_pclmulqdq"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'Q', true },
|
|
// Sandy Bridge microarchitecture based processors.
|
|
{ {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, 'R', false },
|
|
{ {"core_2nd_gen_avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, 'R', true },
|
|
{ {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, '\0', false },
|
|
// Ivy Bridge microarchitecture based processors.
|
|
{ {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', false },
|
|
{ {"core_3rd_gen_avx"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', true },
|
|
{ {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, '\0', false },
|
|
// Haswell microarchitecture based processors.
|
|
{ {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'V', false },
|
|
{ {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, '\0', false },
|
|
{ {"core_4th_gen_avx"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'V', true },
|
|
{ {"core_4th_gen_avx_tsx"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'W', true },
|
|
// Broadwell microarchitecture based processors.
|
|
{ {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'X', false },
|
|
{ {"core_5th_gen_avx"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'X', true },
|
|
{ {"core_5th_gen_avx_tsx"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'Y', true },
|
|
// Skylake client microarchitecture based processors.
|
|
{ {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient, 'b', false },
|
|
// Skylake server microarchitecture based processors.
|
|
{ {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, '\0', false },
|
|
{ {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, '\0', false },
|
|
{ {"skylake_avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, 'a', true },
|
|
// Cascadelake Server microarchitecture based processors.
|
|
{ {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake, '\0', false },
|
|
// Cooperlake Server microarchitecture based processors.
|
|
{ {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake, '\0', false },
|
|
// Cannonlake client microarchitecture based processors.
|
|
{ {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake, 'e', false },
|
|
// Icelake client microarchitecture based processors.
|
|
{ {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient, '\0', false },
|
|
// Rocketlake microarchitecture based processors.
|
|
{ {"rocketlake"}, CK_Rocketlake, FEATURE_AVX512VBMI2, FeaturesRocketlake, '\0', false },
|
|
// Icelake server microarchitecture based processors.
|
|
{ {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer, '\0', false },
|
|
// Tigerlake microarchitecture based processors.
|
|
{ {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake, '\0', false },
|
|
// Sapphire Rapids microarchitecture based processors.
|
|
{ {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, '\0', false },
|
|
// Alderlake microarchitecture based processors.
|
|
{ {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake, '\0', false },
|
|
// Raptorlake microarchitecture based processors.
|
|
{ {"raptorlake"}, CK_Raptorlake, FEATURE_AVX2, FeaturesAlderlake, '\0', false },
|
|
// Meteorlake microarchitecture based processors.
|
|
{ {"meteorlake"}, CK_Meteorlake, FEATURE_AVX2, FeaturesAlderlake, '\0', false },
|
|
// Sierraforest microarchitecture based processors.
|
|
{ {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest, '\0', false },
|
|
// Grandridge microarchitecture based processors.
|
|
{ {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge, '\0', false },
|
|
// Granite Rapids microarchitecture based processors.
|
|
{ {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids, '\0', false },
|
|
// Emerald Rapids microarchitecture based processors.
|
|
{ {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, '\0', false },
|
|
// Knights Landing processor.
|
|
{ {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', false },
|
|
{ {"mic_avx512"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', true },
|
|
// Knights Mill processor.
|
|
{ {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM, 'j', false },
|
|
// Lakemont microarchitecture based processors.
|
|
{ {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B, '\0', false },
|
|
// K6 architecture processors.
|
|
{ {"k6"}, CK_K6, ~0U, FeaturesK6, '\0', false },
|
|
{ {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW, '\0', false },
|
|
{ {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW, '\0', false },
|
|
// K7 architecture processors.
|
|
{ {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon, '\0', false },
|
|
{ {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon, '\0', false },
|
|
{ {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
|
|
{ {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
|
|
{ {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
|
|
// K8 architecture processors.
|
|
{ {"k8"}, CK_K8, ~0U, FeaturesK8, '\0', false },
|
|
{ {"athlon64"}, CK_K8, ~0U, FeaturesK8, '\0', false },
|
|
{ {"athlon-fx"}, CK_K8, ~0U, FeaturesK8, '\0', false },
|
|
{ {"opteron"}, CK_K8, ~0U, FeaturesK8, '\0', false },
|
|
{ {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
|
|
{ {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
|
|
{ {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
|
|
{ {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10, '\0', false },
|
|
{ {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10, '\0', false },
|
|
// Bobcat architecture processors.
|
|
{ {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1, '\0', false },
|
|
{ {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2, '\0', false },
|
|
// Bulldozer architecture processors.
|
|
{ {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1, '\0', false },
|
|
{ {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2, '\0', false },
|
|
{ {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3, '\0', false },
|
|
{ {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4, '\0', false },
|
|
// Zen architecture processors.
|
|
{ {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1, '\0', false },
|
|
{ {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2, '\0', false },
|
|
{ {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3, '\0', false },
|
|
{ {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4, '\0', false },
|
|
// Generic 64-bit processor.
|
|
{ {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64, '\0', false },
|
|
{ {"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2, '\0', false },
|
|
{ {"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3, '\0', false },
|
|
{ {"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4, '\0', false },
|
|
// Geode processors.
|
|
{ {"geode"}, CK_Geode, ~0U, FeaturesGeode, '\0', false },
|
|
};
|
|
|
|
constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
|
|
|
|
X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
|
|
for (const auto &P : Processors)
|
|
if (!P.OnlyForCPUDispatchSpecific && P.Name == CPU &&
|
|
(P.Features[FEATURE_64BIT] || !Only64Bit))
|
|
return P.Kind;
|
|
|
|
return CK_None;
|
|
}
|
|
|
|
X86::CPUKind llvm::X86::parseTuneCPU(StringRef CPU, bool Only64Bit) {
|
|
if (llvm::is_contained(NoTuneList, CPU))
|
|
return CK_None;
|
|
return parseArchX86(CPU, Only64Bit);
|
|
}
|
|
|
|
void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
|
|
bool Only64Bit) {
|
|
for (const auto &P : Processors)
|
|
if (!P.OnlyForCPUDispatchSpecific && !P.Name.empty() &&
|
|
(P.Features[FEATURE_64BIT] || !Only64Bit))
|
|
Values.emplace_back(P.Name);
|
|
}
|
|
|
|
void llvm::X86::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values,
|
|
bool Only64Bit) {
|
|
for (const ProcInfo &P : Processors)
|
|
if (!P.OnlyForCPUDispatchSpecific && !P.Name.empty() &&
|
|
(P.Features[FEATURE_64BIT] || !Only64Bit) &&
|
|
!llvm::is_contained(NoTuneList, P.Name))
|
|
Values.emplace_back(P.Name);
|
|
}
|
|
|
|
ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
|
|
// FIXME: Can we avoid a linear search here? The table might be sorted by
|
|
// CPUKind so we could binary search?
|
|
for (const auto &P : Processors) {
|
|
if (P.Kind == Kind) {
|
|
assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
|
|
return static_cast<ProcessorFeatures>(P.KeyFeature);
|
|
}
|
|
}
|
|
|
|
llvm_unreachable("Unable to find CPU kind!");
|
|
}
|
|
|
|
// Features with no dependencies.
|
|
constexpr FeatureBitset ImpliedFeatures64BIT = {};
|
|
constexpr FeatureBitset ImpliedFeaturesADX = {};
|
|
constexpr FeatureBitset ImpliedFeaturesBMI = {};
|
|
constexpr FeatureBitset ImpliedFeaturesBMI2 = {};
|
|
constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {};
|
|
constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {};
|
|
constexpr FeatureBitset ImpliedFeaturesCLWB = {};
|
|
constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
|
|
constexpr FeatureBitset ImpliedFeaturesCMOV = {};
|
|
constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
|
|
constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
|
|
constexpr FeatureBitset ImpliedFeaturesCRC32 = {};
|
|
constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
|
|
constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
|
|
constexpr FeatureBitset ImpliedFeaturesFXSR = {};
|
|
constexpr FeatureBitset ImpliedFeaturesINVPCID = {};
|
|
constexpr FeatureBitset ImpliedFeaturesLWP = {};
|
|
constexpr FeatureBitset ImpliedFeaturesLZCNT = {};
|
|
constexpr FeatureBitset ImpliedFeaturesMWAITX = {};
|
|
constexpr FeatureBitset ImpliedFeaturesMOVBE = {};
|
|
constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {};
|
|
constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {};
|
|
constexpr FeatureBitset ImpliedFeaturesPCONFIG = {};
|
|
constexpr FeatureBitset ImpliedFeaturesPOPCNT = {};
|
|
constexpr FeatureBitset ImpliedFeaturesPKU = {};
|
|
constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {};
|
|
constexpr FeatureBitset ImpliedFeaturesPRFCHW = {};
|
|
constexpr FeatureBitset ImpliedFeaturesPTWRITE = {};
|
|
constexpr FeatureBitset ImpliedFeaturesRDPID = {};
|
|
constexpr FeatureBitset ImpliedFeaturesRDPRU = {};
|
|
constexpr FeatureBitset ImpliedFeaturesRDRND = {};
|
|
constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
|
|
constexpr FeatureBitset ImpliedFeaturesRTM = {};
|
|
constexpr FeatureBitset ImpliedFeaturesSAHF = {};
|
|
constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
|
|
constexpr FeatureBitset ImpliedFeaturesSGX = {};
|
|
constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
|
|
constexpr FeatureBitset ImpliedFeaturesTBM = {};
|
|
constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {};
|
|
constexpr FeatureBitset ImpliedFeaturesUINTR = {};
|
|
constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
|
|
constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
|
|
constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};
|
|
constexpr FeatureBitset ImpliedFeaturesX87 = {};
|
|
constexpr FeatureBitset ImpliedFeaturesXSAVE = {};
|
|
|
|
// Not really CPU features, but need to be in the table because clang uses
|
|
// target features to communicate them to the backend.
|
|
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {};
|
|
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {};
|
|
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {};
|
|
constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {};
|
|
constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {};
|
|
|
|
// XSAVE features are dependent on basic XSAVE.
|
|
constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
|
|
constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
|
|
constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
|
|
|
|
// MMX->3DNOW->3DNOWA chain.
|
|
constexpr FeatureBitset ImpliedFeaturesMMX = {};
|
|
constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
|
|
constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
|
|
|
|
// SSE/AVX/AVX512F chain.
|
|
constexpr FeatureBitset ImpliedFeaturesSSE = {};
|
|
constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
|
|
constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
|
|
constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
|
|
constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
|
|
constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
|
|
constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
|
|
constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
|
|
constexpr FeatureBitset ImpliedFeaturesAVX512F =
|
|
FeatureAVX2 | FeatureF16C | FeatureFMA;
|
|
|
|
// Vector extensions that build on SSE or AVX.
|
|
constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
|
|
constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
|
|
constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
|
|
constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
|
|
constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
|
|
constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
|
|
constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
|
|
constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
|
|
|
|
// AVX512 features.
|
|
constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
|
|
constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
|
|
constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
|
|
constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
|
|
constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
|
|
constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
|
|
|
|
constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
|
|
constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
|
|
constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
|
|
constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
|
|
constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F;
|
|
constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
|
|
constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
|
|
constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = FeatureAVX512F;
|
|
|
|
// FIXME: These two aren't really implemented and just exist in the feature
|
|
// list for __builtin_cpu_supports. So omit their dependencies.
|
|
constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {};
|
|
constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {};
|
|
|
|
// SSE4_A->FMA4->XOP chain.
|
|
constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
|
|
constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
|
|
constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
|
|
|
|
// AMX Features
|
|
constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
|
|
constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
|
|
constexpr FeatureBitset ImpliedFeaturesAMX_FP16 = FeatureAMX_TILE;
|
|
constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
|
|
constexpr FeatureBitset ImpliedFeaturesAMX_COMPLEX = FeatureAMX_TILE;
|
|
constexpr FeatureBitset ImpliedFeaturesHRESET = {};
|
|
|
|
constexpr FeatureBitset ImpliedFeaturesPREFETCHI = {};
|
|
constexpr FeatureBitset ImpliedFeaturesCMPCCXADD = {};
|
|
constexpr FeatureBitset ImpliedFeaturesRAOINT = {};
|
|
constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT8 = FeatureAVX2;
|
|
constexpr FeatureBitset ImpliedFeaturesAVXIFMA = FeatureAVX2;
|
|
constexpr FeatureBitset ImpliedFeaturesAVXNECONVERT = FeatureAVX2;
|
|
constexpr FeatureBitset ImpliedFeaturesAVX512FP16 =
|
|
FeatureAVX512BW | FeatureAVX512DQ | FeatureAVX512VL;
|
|
// Key Locker Features
|
|
constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
|
|
constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
|
|
|
|
// AVXVNNI Features
|
|
constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
|
|
|
|
constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
|
|
#define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM},
|
|
#include "llvm/TargetParser/X86TargetParser.def"
|
|
};
|
|
|
|
constexpr FeatureInfo FeatureInfos_WithPLUS[X86::CPU_FEATURE_MAX] = {
|
|
#define X86_FEATURE(ENUM, STR) {{"+" STR}, ImpliedFeatures##ENUM},
|
|
#include "llvm/TargetParser/X86TargetParser.def"
|
|
};
|
|
|
|
void llvm::X86::getFeaturesForCPU(StringRef CPU,
|
|
SmallVectorImpl<StringRef> &EnabledFeatures,
|
|
bool IfNeedPlus) {
|
|
auto I = llvm::find_if(Processors,
|
|
[&](const ProcInfo &P) { return P.Name == CPU; });
|
|
assert(I != std::end(Processors) && "Processor not found!");
|
|
|
|
FeatureBitset Bits = I->Features;
|
|
|
|
// Remove the 64-bit feature which we only use to validate if a CPU can
|
|
// be used with 64-bit mode.
|
|
Bits &= ~Feature64BIT;
|
|
|
|
// Add the string version of all set bits.
|
|
for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
|
|
if (Bits[i] && !FeatureInfos[i].Name.empty() &&
|
|
!FeatureInfos_WithPLUS[i].Name.empty()){
|
|
EnabledFeatures.push_back(IfNeedPlus ? FeatureInfos_WithPLUS[i].Name
|
|
: FeatureInfos[i].Name);
|
|
}
|
|
}
|
|
|
|
// For each feature that is (transitively) implied by this feature, set it.
|
|
static void getImpliedEnabledFeatures(FeatureBitset &Bits,
|
|
const FeatureBitset &Implies) {
|
|
// Fast path: Implies is often empty.
|
|
if (!Implies.any())
|
|
return;
|
|
FeatureBitset Prev;
|
|
Bits |= Implies;
|
|
do {
|
|
Prev = Bits;
|
|
for (unsigned i = CPU_FEATURE_MAX; i;)
|
|
if (Bits[--i])
|
|
Bits |= FeatureInfos[i].ImpliedFeatures;
|
|
} while (Prev != Bits);
|
|
}
|
|
|
|
/// Create bit vector of features that are implied disabled if the feature
|
|
/// passed in Value is disabled.
|
|
static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
|
|
// Check all features looking for any dependent on this feature. If we find
|
|
// one, mark it and recursively find any feature that depend on it.
|
|
FeatureBitset Prev;
|
|
Bits.set(Value);
|
|
do {
|
|
Prev = Bits;
|
|
for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
|
|
if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
|
|
Bits.set(i);
|
|
} while (Prev != Bits);
|
|
}
|
|
|
|
void llvm::X86::updateImpliedFeatures(
|
|
StringRef Feature, bool Enabled,
|
|
StringMap<bool> &Features) {
|
|
auto I = llvm::find_if(
|
|
FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; });
|
|
if (I == std::end(FeatureInfos)) {
|
|
// FIXME: This shouldn't happen, but may not have all features in the table
|
|
// yet.
|
|
return;
|
|
}
|
|
|
|
FeatureBitset ImpliedBits;
|
|
if (Enabled)
|
|
getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
|
|
else
|
|
getImpliedDisabledFeatures(ImpliedBits,
|
|
std::distance(std::begin(FeatureInfos), I));
|
|
|
|
// Update the map entry for all implied features.
|
|
for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
|
|
if (ImpliedBits[i] && !FeatureInfos[i].Name.empty())
|
|
Features[FeatureInfos[i].Name] = Enabled;
|
|
}
|
|
|
|
char llvm::X86::getCPUDispatchMangling(StringRef CPU) {
|
|
auto I = llvm::find_if(Processors,
|
|
[&](const ProcInfo &P) { return P.Name == CPU; });
|
|
assert(I != std::end(Processors) && "Processor not found!");
|
|
assert(I->Mangling != '\0' && "Processor dooesn't support function multiversion!");
|
|
return I->Mangling;
|
|
}
|
|
|
|
bool llvm::X86::validateCPUSpecificCPUDispatch(StringRef Name) {
|
|
auto I = llvm::find_if(Processors,
|
|
[&](const ProcInfo &P) { return P.Name == Name; });
|
|
return I != std::end(Processors);
|
|
}
|
|
|
|
uint64_t llvm::X86::getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs) {
|
|
// Processor features and mapping to processor feature value.
|
|
uint64_t FeaturesMask = 0;
|
|
for (const StringRef &FeatureStr : FeatureStrs) {
|
|
unsigned Feature = StringSwitch<unsigned>(FeatureStr)
|
|
#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
|
|
.Case(STR, llvm::X86::FEATURE_##ENUM)
|
|
#include "llvm/TargetParser/X86TargetParser.def"
|
|
;
|
|
FeaturesMask |= (1ULL << Feature);
|
|
}
|
|
return FeaturesMask;
|
|
}
|
|
|
|
unsigned llvm::X86::getFeaturePriority(ProcessorFeatures Feat) {
|
|
#ifndef NDEBUG
|
|
// Check that priorities are set properly in the .def file. We expect that
|
|
// "compat" features are assigned non-duplicate consecutive priorities
|
|
// starting from zero (0, 1, ..., num_features - 1).
|
|
#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY,
|
|
unsigned Priorities[] = {
|
|
#include "llvm/TargetParser/X86TargetParser.def"
|
|
std::numeric_limits<unsigned>::max() // Need to consume last comma.
|
|
};
|
|
std::array<unsigned, std::size(Priorities) - 1> HelperList;
|
|
std::iota(HelperList.begin(), HelperList.end(), 0);
|
|
assert(std::is_permutation(HelperList.begin(), HelperList.end(),
|
|
std::begin(Priorities),
|
|
std::prev(std::end(Priorities))) &&
|
|
"Priorities don't form consecutive range!");
|
|
#endif
|
|
|
|
switch (Feat) {
|
|
#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
|
|
case X86::FEATURE_##ENUM: \
|
|
return PRIORITY;
|
|
#include "llvm/TargetParser/X86TargetParser.def"
|
|
default:
|
|
llvm_unreachable("No Feature Priority for non-CPUSupports Features");
|
|
}
|
|
}
|