Files
clang-p2996/llvm/test/CodeGen/AArch64
Harvin Iriawan c35d2071d8 [AArch64] NFC : Change the way SVE pseudos are appended
* SVE pseudos don't pick up the right latency information during MI
    scheduling as the regex do not match with instruction name.

  * Move UNDEF, PSEUDO, and ZERO to the end of actual SVE instruction

  * Some CPUs *td files will be fixed in the next commit

    Differential Revision: https://reviews.llvm.org/D154232
2023-07-04 10:41:56 +01:00
..
2023-01-24 22:36:39 +01:00
2023-03-23 20:20:20 -07:00
2023-01-24 22:36:39 +01:00

++ SVE CodeGen Warnings ++

When the WARN check lines fail in the SVE codegen tests it most likely means you
have introduced a warning due to:
1. Adding an invalid call to VectorType::getNumElements() or EVT::getVectorNumElements()
   when the type is a scalable vector.
2. Relying upon an implicit cast conversion from TypeSize to uint64_t.

For generic code, please modify your code to work with ElementCount and TypeSize directly.
For target-specific code that only deals with fixed-width vectors, use the fixed-size interfaces.
Please refer to the code where those functions live for more details.