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clang-p2996/llvm/lib/Target/AArch64
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Jon Roelofs 75187aa352 [AArch64][GlobalISel] Legalize ctpop for v2s64, v2s32, v4s32, v4s16, v8s16 
https://llvm.godbolt.org/z/nTTK6M5qe

Differential revision: https://reviews.llvm.org/D106388
2021-07-20 15:37:56 -07:00
..
AsmParser
[AArch64][SME] Add system registers and related instructions
2021-07-20 08:06:26 +00:00
Disassembler
[AArch64][SME] Add system registers and related instructions
2021-07-20 08:06:26 +00:00
GISel
[AArch64][GlobalISel] Legalize ctpop for v2s64, v2s32, v4s32, v4s16, v8s16
2021-07-20 15:37:56 -07:00
MCTargetDesc
[AArch64][SME] Add system registers and related instructions
2021-07-20 08:06:26 +00:00
TargetInfo
…
Utils
[AArch64][SME] Add system registers and related instructions
2021-07-20 08:06:26 +00:00
AArch64.h
[AArch64][GlobalISel] Create a new minimal combiner pass just for -O0.
2021-05-07 17:01:27 -07:00
AArch64.td
[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)
2021-07-12 13:28:10 +00:00
AArch64A53Fix835769.cpp
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AArch64A57FPLoadBalancing.cpp
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AArch64AdvSIMDScalarPass.cpp
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AArch64AsmPrinter.cpp
[AArch64] De-capitalize some Emit* functions
2021-07-11 22:05:39 -07:00
AArch64BranchTargets.cpp
[AArch64] Fix for BTI landing pad insertion with PAC-RET+bkey.
2021-04-23 10:07:25 +02:00
AArch64CallingConvention.cpp
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AArch64CallingConvention.h
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AArch64CallingConvention.td
IR/AArch64/X86: add "swifttailcc" calling convention.
2021-05-17 10:48:34 +01:00
AArch64CleanupLocalDynamicTLSPass.cpp
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AArch64CollectLOH.cpp
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AArch64Combine.td
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
AArch64CompressJumpTables.cpp
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AArch64CondBrTuning.cpp
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AArch64ConditionalCompares.cpp
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AArch64ConditionOptimizer.cpp
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AArch64DeadRegisterDefinitionsPass.cpp
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AArch64ExpandImm.cpp
[AArch64] Fix some coding standard issues related to namespace llvm
2021-05-05 15:27:16 -07:00
AArch64ExpandImm.h
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AArch64ExpandPseudoInsts.cpp
[AArch64] Fix i128 cmpxchg using ldxp/stxp.
2021-07-20 12:38:12 -07:00
AArch64FalkorHWPFFix.cpp
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AArch64FastISel.cpp
[AArch64] Optimize overflow checks for [s|u]mul.with.overflow.i32.
2021-07-12 15:30:42 -07:00
AArch64FrameLowering.cpp
[AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP)
2021-06-24 18:24:32 +01:00
AArch64FrameLowering.h
[NFC] Fix a few whitespace issues and typos.
2021-07-04 11:49:58 +01:00
AArch64GenRegisterBankInfo.def
AArch64: support i128 cmpxchg in GlobalISel.
2021-05-14 10:41:38 +01:00
AArch64InstrAtomics.td
[AArch64] Fix i128 cmpxchg using ldxp/stxp.
2021-07-20 12:38:12 -07:00
AArch64InstrFormats.td
[AArch64][SME] Add load and store instructions
2021-07-16 10:11:10 +00:00
AArch64InstrGISel.td
AArch64: support i128 cmpxchg in GlobalISel.
2021-05-14 10:41:38 +01:00
AArch64InstrInfo.cpp
[AArch64] Dump a little more info about unimplemented reg-to-reg copies. NFC
2021-07-12 15:37:11 -07:00
AArch64InstrInfo.h
[NFC] Fix a few whitespace issues and typos.
2021-07-04 11:49:58 +01:00
AArch64InstrInfo.td
[AArch64][SME] Add matrix register definitions and parsing support
2021-07-14 08:25:49 +00:00
AArch64ISelDAGToDAG.cpp
[CodeGen][AArch64][SVE] Use ld1r[bhsd] for vector splat from memory
2021-07-06 12:03:54 +00:00
AArch64ISelLowering.cpp
[AArch64] Use the CMP_SWAP_128 variants added in 843c6140.
2021-07-20 13:23:27 -07:00
AArch64ISelLowering.h
[ARM] Remove PromotedBitwiseVT for NEON types
2021-07-19 16:36:33 +01:00
AArch64LoadStoreOptimizer.cpp
Revert "[AArch64LoadStoreOptimizer] Recommit: Generate more STPs by renaming registers earlier"
2021-06-23 09:54:16 +03:00
AArch64LowerHomogeneousPrologEpilog.cpp
[CodeGen] Add missing includes (NFC)
2021-06-06 15:48:27 +02:00
AArch64MachineFunctionInfo.cpp
[llvm] Rename StringRef _lower() method calls to _insensitive()
2021-06-25 00:22:01 +03:00
AArch64MachineFunctionInfo.h
IR/AArch64/X86: add "swifttailcc" calling convention.
2021-05-17 10:48:34 +01:00
AArch64MacroFusion.cpp
[AArch64] Fix some coding standard issues related to namespace llvm
2021-05-05 15:27:16 -07:00
AArch64MacroFusion.h
…
AArch64MCInstLower.cpp
[AArch64][ELF] Prefer to lower MC_GlobalAddress operands to .Lfoo$local
2021-05-07 09:44:26 -07:00
AArch64MCInstLower.h
…
AArch64PBQPRegAlloc.cpp
[NFCI] Move DEBUG_TYPE definition below #includes
2021-05-30 17:31:01 +08:00
AArch64PBQPRegAlloc.h
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AArch64PerfectShuffle.h
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AArch64PfmCounters.td
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AArch64PromoteConstant.cpp
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AArch64RedundantCopyElimination.cpp
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AArch64RegisterBanks.td
AArch64: support i128 cmpxchg in GlobalISel.
2021-05-14 10:41:38 +01:00
AArch64RegisterInfo.cpp
[AArch64][SME] Add load and store instructions
2021-07-16 10:11:10 +00:00
AArch64RegisterInfo.h
…
AArch64RegisterInfo.td
[AArch64][SME] Add system registers and related instructions
2021-07-20 08:06:26 +00:00
AArch64SchedA53.td
[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)
2021-07-12 13:28:10 +00:00
AArch64SchedA55.td
[AArch64] Update Cortex-A55 SchedModel to improve LDP scheduling
2021-07-16 12:00:57 +01:00
AArch64SchedA57.td
[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)
2021-07-12 13:28:10 +00:00
AArch64SchedA57WriteRes.td
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AArch64SchedA64FX.td
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AArch64SchedCyclone.td
[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)
2021-07-12 13:28:10 +00:00
AArch64SchedExynosM3.td
[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)
2021-07-12 13:28:10 +00:00
AArch64SchedExynosM4.td
[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)
2021-07-12 13:28:10 +00:00
AArch64SchedExynosM5.td
[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)
2021-07-12 13:28:10 +00:00
AArch64SchedFalkor.td
[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)
2021-07-12 13:28:10 +00:00
AArch64SchedFalkorDetails.td
…
AArch64SchedKryo.td
[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)
2021-07-12 13:28:10 +00:00
AArch64SchedKryoDetails.td
…
AArch64SchedPredExynos.td
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AArch64SchedPredicates.td
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AArch64SchedThunderX2T99.td
[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)
2021-07-12 13:28:10 +00:00
AArch64SchedThunderX3T110.td
…
AArch64SchedThunderX.td
[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)
2021-07-12 13:28:10 +00:00
AArch64SchedTSV110.td
…
AArch64Schedule.td
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AArch64SelectionDAGInfo.cpp
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AArch64SelectionDAGInfo.h
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AArch64SIMDInstrOpt.cpp
…
AArch64SLSHardening.cpp
[ARM][AArch64] SLSHardening: make non-comdat thunks possible
2021-05-20 17:07:05 +02:00
AArch64SMEInstrInfo.td
[AArch64][SME] Add system registers and related instructions
2021-07-20 08:06:26 +00:00
AArch64SpeculationHardening.cpp
…
AArch64StackTagging.cpp
[NFC] [MTE] helper for stack tagging lifetimes.
2021-07-19 11:09:16 +01:00
AArch64StackTaggingPreRA.cpp
[AArch64] Fix some coding standard issues related to namespace llvm
2021-05-05 15:27:16 -07:00
AArch64StorePairSuppress.cpp
…
AArch64Subtarget.cpp
[AArch64][SVE] Wire up vscale_range attribute to SVE min/max vector queries
2021-06-21 13:00:36 +01:00
AArch64Subtarget.h
[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)
2021-07-12 13:28:10 +00:00
AArch64SVEInstrInfo.td
[AArch64][SVE] Add ISel patterns for floating point compare with zero instructions
2021-07-08 10:46:12 +00:00
AArch64SystemOperands.td
[AArch64][SME] Add system registers and related instructions
2021-07-20 08:06:26 +00:00
AArch64TargetMachine.cpp
Fix typo in help text for -aarch64-enable-branch-targets.
2021-07-05 16:15:40 +01:00
AArch64TargetMachine.h
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AArch64TargetObjectFile.cpp
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AArch64TargetObjectFile.h
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AArch64TargetTransformInfo.cpp
[AArch64][SVE] Move instcombine like transforms out of SVEIntrinsicOpts
2021-07-20 14:17:30 +00:00
AArch64TargetTransformInfo.h
[TTI] Consistently make getMinVectorRegisterBitWidth() methods const. NFCI.
2021-07-15 13:27:55 +01:00
CMakeLists.txt
[AArch64][GlobalISel] Create a new minimal combiner pass just for -O0.
2021-05-07 17:01:27 -07:00
SMEInstrFormats.td
[AArch64][SME] Add SVE2 instructions added in SME
2021-07-19 08:03:05 +00:00
SVEInstrFormats.td
[AArch64] Prepare for changes to STEP_VECTOR.
2021-07-17 14:13:41 -07:00
SVEIntrinsicOpts.cpp
[AArch64][SVE] Move instcombine like transforms out of SVEIntrinsicOpts
2021-07-20 14:17:30 +00:00