c23a780c30
And a small utilities -- extract-section.py -- that helps extracting specific object file section and printing in textual format. This utility is just a workaround for tests inside `Encoding`. Hopefully in the future we can replace dependencies in those tests with existing tools (e.g. llvm-readobj). Please refer to this bug for more context: https://bugs.llvm.org/show_bug.cgi?id=49245 Note that since we don't have AsmParser for now, we are testing the MC part using MIR as input and put those tests under the `Encoding` folder. In the future when AsmParser (and disassembler) is finished, those tests will be moved to `test/MC/M68k`. Authors: myhsu, m4yers, glaubitz Differential Revision: https://reviews.llvm.org/D88392
115 lines
3.6 KiB
YAML
115 lines
3.6 KiB
YAML
# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj \
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# RUN: -code-model=small -relocation-model=pic -o - \
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# RUN: | extract-section .text -h \
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# RUN: | FileCheck %s
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#------------------------------------------------------------------------------
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# Test branch relaxation. By default codegen choses smallest branch instruction,
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# during object code generation it might get clear that offset does not fit and
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# bigger instruction is required.
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#------------------------------------------------------------------------------
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--- # TIGHT
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# The offset for the small branch is from the PC value, which points to the
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# next instruction, because there is no extension word here.
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# 000 CHECK: 6078
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# 002 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 00C CHECK-SAME: 23f9 0000 0000 0000 0000
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# 016 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 020 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 02A CHECK-SAME: 23f9 0000 0000 0000 0000
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# 034 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 03E CHECK-SAME: 23f9 0000 0000 0000 0000
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# 048 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 052 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 05C CHECK-SAME: 23f9 0000 0000 0000 0000
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# 066 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 070 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 07A CHECK-SAME: d0bc 0000 0000
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# 080 CHECK-SAME: 4e75
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name: TIGHT
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body: |
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bb.0:
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successors: %bb.2
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BRA8 %bb.2
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bb.1:
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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bb.2:
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$d0 = ADD32ri $d0, 0, implicit-def $ccr
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RET 0, $d0
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...
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--- # RELAXED
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# 084 CHECK-SAME 6000 0084
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# 088 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 092 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 09C CHECK-SAME: 23f9 0000 0000 0000 0000
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# 0A6 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 0B0 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 0BA CHECK-SAME: 23f9 0000 0000 0000 0000
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# 0C4 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 0CE CHECK-SAME: 23f9 0000 0000 0000 0000
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# 0D8 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 0E2 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 0EC CHECK-SAME: 23f9 0000 0000 0000 0000
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# 0F6 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 100 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 10A CHECK-SAME: d0bc 0000 0000
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# 110 CHECK-SAME: 4e75
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name: RELAXED
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body: |
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bb.0:
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successors: %bb.2
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BRA8 %bb.2
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bb.1:
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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bb.2:
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$d0 = ADD32ri $d0, 0, implicit-def $ccr
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RET 0, $d0
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...
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--- # ZERO
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# Because of the way M68k encodes branches it is not possible to encode 0
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# offset with the smallest insruction(0 in the offset field means exension word
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# is used) thus we switch to the wider instruction.
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# 114 CHECK-SAME: 6000 0002
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# 118 CHECK-SAME: d0bc 0000 0000
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# 11E CHECK-SAME: 4e75
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name: ZERO
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body: |
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bb.0:
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successors: %bb.1
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BRA8 %bb.1
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bb.1:
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$d0 = ADD32ri $d0, 0, implicit-def $ccr
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RET 0, $d0
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...
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