173332d175
We assume VLENB is a multiple of 8 and previously relied on shift pairs being optimized to an AND+SHL/SHR and computeKnownBits removing the AND. This doesn't happen if (vlenb >> 3) gets CSEd to have multiple uses. This patch manually emits the best shift to workaround this.
517 lines
17 KiB
LLVM
517 lines
17 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs < %s | FileCheck %s
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declare <vscale x 1 x i8> @llvm.experimental.stepvector.nxv1i8()
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define <vscale x 1 x i8> @stepvector_nxv1i8() {
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; CHECK-LABEL: stepvector_nxv1i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 1 x i8> @llvm.experimental.stepvector.nxv1i8()
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ret <vscale x 1 x i8> %v
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}
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declare <vscale x 2 x i8> @llvm.experimental.stepvector.nxv2i8()
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define <vscale x 2 x i8> @stepvector_nxv2i8() {
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; CHECK-LABEL: stepvector_nxv2i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i8> @llvm.experimental.stepvector.nxv2i8()
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ret <vscale x 2 x i8> %v
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}
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declare <vscale x 4 x i8> @llvm.experimental.stepvector.nxv4i8()
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define <vscale x 4 x i8> @stepvector_nxv4i8() {
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; CHECK-LABEL: stepvector_nxv4i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 4 x i8> @llvm.experimental.stepvector.nxv4i8()
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ret <vscale x 4 x i8> %v
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}
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declare <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
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define <vscale x 8 x i8> @stepvector_nxv8i8() {
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; CHECK-LABEL: stepvector_nxv8i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
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ret <vscale x 8 x i8> %v
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}
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define <vscale x 8 x i8> @add_stepvector_nxv8i8() {
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; CHECK-LABEL: add_stepvector_nxv8i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
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; CHECK-NEXT: vid.v v25
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; CHECK-NEXT: vsll.vi v8, v25, 1
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; CHECK-NEXT: ret
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entry:
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%0 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
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%1 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
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%2 = add <vscale x 8 x i8> %0, %1
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ret <vscale x 8 x i8> %2
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}
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define <vscale x 8 x i8> @mul_stepvector_nxv8i8() {
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; CHECK-LABEL: mul_stepvector_nxv8i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
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; CHECK-NEXT: vid.v v25
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; CHECK-NEXT: addi a0, zero, 3
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; CHECK-NEXT: vmul.vx v8, v25, a0
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; CHECK-NEXT: ret
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entry:
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%0 = insertelement <vscale x 8 x i8> poison, i8 3, i32 0
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%1 = shufflevector <vscale x 8 x i8> %0, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
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%2 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
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%3 = mul <vscale x 8 x i8> %2, %1
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ret <vscale x 8 x i8> %3
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}
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define <vscale x 8 x i8> @shl_stepvector_nxv8i8() {
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; CHECK-LABEL: shl_stepvector_nxv8i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
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; CHECK-NEXT: vid.v v25
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; CHECK-NEXT: vsll.vi v8, v25, 2
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; CHECK-NEXT: ret
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entry:
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%0 = insertelement <vscale x 8 x i8> poison, i8 2, i32 0
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%1 = shufflevector <vscale x 8 x i8> %0, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
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%2 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
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%3 = shl <vscale x 8 x i8> %2, %1
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ret <vscale x 8 x i8> %3
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}
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declare <vscale x 16 x i8> @llvm.experimental.stepvector.nxv16i8()
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define <vscale x 16 x i8> @stepvector_nxv16i8() {
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; CHECK-LABEL: stepvector_nxv16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i8> @llvm.experimental.stepvector.nxv16i8()
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ret <vscale x 16 x i8> %v
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}
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declare <vscale x 32 x i8> @llvm.experimental.stepvector.nxv32i8()
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define <vscale x 32 x i8> @stepvector_nxv32i8() {
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; CHECK-LABEL: stepvector_nxv32i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 32 x i8> @llvm.experimental.stepvector.nxv32i8()
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ret <vscale x 32 x i8> %v
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}
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declare <vscale x 64 x i8> @llvm.experimental.stepvector.nxv64i8()
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define <vscale x 64 x i8> @stepvector_nxv64i8() {
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; CHECK-LABEL: stepvector_nxv64i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 64 x i8> @llvm.experimental.stepvector.nxv64i8()
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ret <vscale x 64 x i8> %v
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}
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declare <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
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define <vscale x 1 x i16> @stepvector_nxv1i16() {
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; CHECK-LABEL: stepvector_nxv1i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
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ret <vscale x 1 x i16> %v
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}
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declare <vscale x 2 x i16> @llvm.experimental.stepvector.nxv2i16()
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define <vscale x 2 x i16> @stepvector_nxv2i16() {
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; CHECK-LABEL: stepvector_nxv2i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i16> @llvm.experimental.stepvector.nxv2i16()
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ret <vscale x 2 x i16> %v
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}
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declare <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16()
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define <vscale x 4 x i16> @stepvector_nxv4i16() {
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; CHECK-LABEL: stepvector_nxv4i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16()
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ret <vscale x 4 x i16> %v
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}
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declare <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16()
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define <vscale x 8 x i16> @stepvector_nxv8i16() {
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; CHECK-LABEL: stepvector_nxv8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16()
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ret <vscale x 8 x i16> %v
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}
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declare <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
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define <vscale x 16 x i16> @stepvector_nxv16i16() {
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; CHECK-LABEL: stepvector_nxv16i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
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ret <vscale x 16 x i16> %v
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}
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define <vscale x 16 x i16> @add_stepvector_nxv16i16() {
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; CHECK-LABEL: add_stepvector_nxv16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
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; CHECK-NEXT: vid.v v28
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; CHECK-NEXT: vsll.vi v8, v28, 1
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; CHECK-NEXT: ret
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entry:
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%0 = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
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%1 = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
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%2 = add <vscale x 16 x i16> %0, %1
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ret <vscale x 16 x i16> %2
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}
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define <vscale x 16 x i16> @mul_stepvector_nxv16i16() {
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; CHECK-LABEL: mul_stepvector_nxv16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
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; CHECK-NEXT: vid.v v28
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; CHECK-NEXT: addi a0, zero, 3
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; CHECK-NEXT: vmul.vx v8, v28, a0
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; CHECK-NEXT: ret
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entry:
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%0 = insertelement <vscale x 16 x i16> poison, i16 3, i32 0
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%1 = shufflevector <vscale x 16 x i16> %0, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
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%2 = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
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%3 = mul <vscale x 16 x i16> %2, %1
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ret <vscale x 16 x i16> %3
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}
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define <vscale x 16 x i16> @shl_stepvector_nxv16i16() {
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; CHECK-LABEL: shl_stepvector_nxv16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
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; CHECK-NEXT: vid.v v28
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; CHECK-NEXT: vsll.vi v8, v28, 2
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; CHECK-NEXT: ret
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entry:
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%0 = insertelement <vscale x 16 x i16> poison, i16 2, i32 0
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%1 = shufflevector <vscale x 16 x i16> %0, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
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%2 = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
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%3 = shl <vscale x 16 x i16> %2, %1
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ret <vscale x 16 x i16> %3
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}
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declare <vscale x 32 x i16> @llvm.experimental.stepvector.nxv32i16()
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define <vscale x 32 x i16> @stepvector_nxv32i16() {
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; CHECK-LABEL: stepvector_nxv32i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 32 x i16> @llvm.experimental.stepvector.nxv32i16()
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ret <vscale x 32 x i16> %v
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}
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declare <vscale x 1 x i32> @llvm.experimental.stepvector.nxv1i32()
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define <vscale x 1 x i32> @stepvector_nxv1i32() {
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; CHECK-LABEL: stepvector_nxv1i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 1 x i32> @llvm.experimental.stepvector.nxv1i32()
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ret <vscale x 1 x i32> %v
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}
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declare <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32()
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define <vscale x 2 x i32> @stepvector_nxv2i32() {
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; CHECK-LABEL: stepvector_nxv2i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32()
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ret <vscale x 2 x i32> %v
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}
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declare <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
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define <vscale x 4 x i32> @stepvector_nxv4i32() {
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; CHECK-LABEL: stepvector_nxv4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
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ret <vscale x 4 x i32> %v
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}
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declare <vscale x 8 x i32> @llvm.experimental.stepvector.nxv8i32()
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define <vscale x 8 x i32> @stepvector_nxv8i32() {
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; CHECK-LABEL: stepvector_nxv8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 8 x i32> @llvm.experimental.stepvector.nxv8i32()
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ret <vscale x 8 x i32> %v
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}
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declare <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
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define <vscale x 16 x i32> @stepvector_nxv16i32() {
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; CHECK-LABEL: stepvector_nxv16i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
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ret <vscale x 16 x i32> %v
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}
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define <vscale x 16 x i32> @add_stepvector_nxv16i32() {
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; CHECK-LABEL: add_stepvector_nxv16i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: vsll.vi v8, v8, 1
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; CHECK-NEXT: ret
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entry:
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%0 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
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%1 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
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%2 = add <vscale x 16 x i32> %0, %1
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ret <vscale x 16 x i32> %2
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}
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define <vscale x 16 x i32> @mul_stepvector_nxv16i32() {
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; CHECK-LABEL: mul_stepvector_nxv16i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: addi a0, zero, 3
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; CHECK-NEXT: vmul.vx v8, v8, a0
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; CHECK-NEXT: ret
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entry:
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%0 = insertelement <vscale x 16 x i32> poison, i32 3, i32 0
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%1 = shufflevector <vscale x 16 x i32> %0, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
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%2 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
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%3 = mul <vscale x 16 x i32> %2, %1
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ret <vscale x 16 x i32> %3
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}
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define <vscale x 16 x i32> @shl_stepvector_nxv16i32() {
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; CHECK-LABEL: shl_stepvector_nxv16i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: vsll.vi v8, v8, 2
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; CHECK-NEXT: ret
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entry:
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%0 = insertelement <vscale x 16 x i32> poison, i32 2, i32 0
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%1 = shufflevector <vscale x 16 x i32> %0, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
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%2 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
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%3 = shl <vscale x 16 x i32> %2, %1
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ret <vscale x 16 x i32> %3
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}
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declare <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
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define <vscale x 1 x i64> @stepvector_nxv1i64() {
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; CHECK-LABEL: stepvector_nxv1i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
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ret <vscale x 1 x i64> %v
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}
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declare <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
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define <vscale x 2 x i64> @stepvector_nxv2i64() {
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; CHECK-LABEL: stepvector_nxv2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
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ret <vscale x 2 x i64> %v
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}
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declare <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64()
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define <vscale x 4 x i64> @stepvector_nxv4i64() {
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; CHECK-LABEL: stepvector_nxv4i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64()
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ret <vscale x 4 x i64> %v
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}
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declare <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64()
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define <vscale x 8 x i64> @stepvector_nxv8i64() {
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; CHECK-LABEL: stepvector_nxv8i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64()
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ret <vscale x 8 x i64> %v
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}
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define <vscale x 8 x i64> @add_stepvector_nxv8i64() {
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; CHECK-LABEL: add_stepvector_nxv8i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: vsll.vi v8, v8, 1
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; CHECK-NEXT: ret
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entry:
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%0 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64()
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%1 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64()
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%2 = add <vscale x 8 x i64> %0, %1
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ret <vscale x 8 x i64> %2
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}
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define <vscale x 8 x i64> @mul_stepvector_nxv8i64() {
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; CHECK-LABEL: mul_stepvector_nxv8i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: addi a0, zero, 3
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; CHECK-NEXT: vmul.vx v8, v8, a0
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; CHECK-NEXT: ret
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entry:
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%0 = insertelement <vscale x 8 x i64> poison, i64 3, i32 0
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%1 = shufflevector <vscale x 8 x i64> %0, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
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%2 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64()
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%3 = mul <vscale x 8 x i64> %2, %1
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ret <vscale x 8 x i64> %3
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}
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define <vscale x 8 x i64> @shl_stepvector_nxv8i64() {
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; CHECK-LABEL: shl_stepvector_nxv8i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: vsll.vi v8, v8, 2
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; CHECK-NEXT: ret
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entry:
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%0 = insertelement <vscale x 8 x i64> poison, i64 2, i32 0
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%1 = shufflevector <vscale x 8 x i64> %0, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
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%2 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64()
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%3 = shl <vscale x 8 x i64> %2, %1
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ret <vscale x 8 x i64> %3
|
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}
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|
|
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declare <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
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|
|
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define <vscale x 16 x i64> @stepvector_nxv16i64() {
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; CHECK-LABEL: stepvector_nxv16i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
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|
; CHECK-NEXT: vid.v v8
|
|
; CHECK-NEXT: vadd.vx v16, v8, a0
|
|
; CHECK-NEXT: ret
|
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%v = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
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|
ret <vscale x 16 x i64> %v
|
|
}
|
|
|
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define <vscale x 16 x i64> @add_stepvector_nxv16i64() {
|
|
; CHECK-LABEL: add_stepvector_nxv16i64:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a0, a0, 1
|
|
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
|
|
; CHECK-NEXT: vid.v v8
|
|
; CHECK-NEXT: vsll.vi v8, v8, 1
|
|
; CHECK-NEXT: vadd.vx v16, v8, a0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%0 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
|
|
%1 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
|
|
%2 = add <vscale x 16 x i64> %0, %1
|
|
ret <vscale x 16 x i64> %2
|
|
}
|
|
|
|
define <vscale x 16 x i64> @mul_stepvector_nxv16i64() {
|
|
; CHECK-LABEL: mul_stepvector_nxv16i64:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
|
|
; CHECK-NEXT: vid.v v8
|
|
; CHECK-NEXT: addi a0, zero, 3
|
|
; CHECK-NEXT: vmul.vx v8, v8, a0
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a1, a0, 1
|
|
; CHECK-NEXT: add a0, a1, a0
|
|
; CHECK-NEXT: vadd.vx v16, v8, a0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%0 = insertelement <vscale x 16 x i64> poison, i64 3, i32 0
|
|
%1 = shufflevector <vscale x 16 x i64> %0, <vscale x 16 x i64> poison, <vscale x 16 x i32> zeroinitializer
|
|
%2 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
|
|
%3 = mul <vscale x 16 x i64> %2, %1
|
|
ret <vscale x 16 x i64> %3
|
|
}
|
|
|
|
define <vscale x 16 x i64> @shl_stepvector_nxv16i64() {
|
|
; CHECK-LABEL: shl_stepvector_nxv16i64:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a0, a0, 2
|
|
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
|
|
; CHECK-NEXT: vid.v v8
|
|
; CHECK-NEXT: vsll.vi v8, v8, 2
|
|
; CHECK-NEXT: vadd.vx v16, v8, a0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%0 = insertelement <vscale x 16 x i64> poison, i64 2, i32 0
|
|
%1 = shufflevector <vscale x 16 x i64> %0, <vscale x 16 x i64> poison, <vscale x 16 x i32> zeroinitializer
|
|
%2 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
|
|
%3 = shl <vscale x 16 x i64> %2, %1
|
|
ret <vscale x 16 x i64> %3
|
|
}
|