ea87cf2acd
RISCV has to use 2 shifts for (i64 (zext_inreg X, i32)), but we can use addiw rd, rs1, x0 for sext_inreg. We already understood this when type legalizing i32 seteq/ne on rv64. But this transform in SimplifySetCC would sometimes undo it. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D95289
122 lines
3.2 KiB
LLVM
122 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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define i1 @and_icmp_eq(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; RV32I-LABEL: and_icmp_eq:
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; RV32I: # %bb.0:
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: xor a1, a2, a3
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: seqz a0, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_icmp_eq:
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; RV64I: # %bb.0:
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: xor a1, a2, a3
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: seqz a0, a0
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; RV64I-NEXT: ret
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%cmp1 = icmp eq i32 %a, %b
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%cmp2 = icmp eq i32 %c, %d
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%and = and i1 %cmp1, %cmp2
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ret i1 %and
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}
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define i1 @or_icmp_ne(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; RV32I-LABEL: or_icmp_ne:
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; RV32I: # %bb.0:
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: xor a1, a2, a3
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: snez a0, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: or_icmp_ne:
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; RV64I: # %bb.0:
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: xor a1, a2, a3
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: snez a0, a0
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; RV64I-NEXT: ret
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%cmp1 = icmp ne i32 %a, %b
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%cmp2 = icmp ne i32 %c, %d
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%or = or i1 %cmp1, %cmp2
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ret i1 %or
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}
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define i1 @or_icmps_const_1bit_diff(i64 %x) nounwind {
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; RV32I-LABEL: or_icmps_const_1bit_diff:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a2, a0, -13
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; RV32I-NEXT: sltu a0, a2, a0
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; RV32I-NEXT: add a0, a1, a0
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: andi a1, a2, -5
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; RV32I-NEXT: or a0, a1, a0
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; RV32I-NEXT: seqz a0, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: or_icmps_const_1bit_diff:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, -13
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; RV64I-NEXT: andi a0, a0, -5
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; RV64I-NEXT: seqz a0, a0
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; RV64I-NEXT: ret
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%a = icmp eq i64 %x, 17
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%b = icmp eq i64 %x, 13
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%r = or i1 %a, %b
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ret i1 %r
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}
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define i1 @and_icmps_const_1bit_diff(i32 %x) nounwind {
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; RV32I-LABEL: and_icmps_const_1bit_diff:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, -44
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; RV32I-NEXT: andi a0, a0, -17
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; RV32I-NEXT: snez a0, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_icmps_const_1bit_diff:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, -44
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; RV64I-NEXT: andi a0, a0, -17
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: snez a0, a0
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; RV64I-NEXT: ret
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%a = icmp ne i32 %x, 44
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%b = icmp ne i32 %x, 60
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%r = and i1 %a, %b
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ret i1 %r
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}
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define i1 @and_icmps_const_not1bit_diff(i32 %x) nounwind {
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; RV32I-LABEL: and_icmps_const_not1bit_diff:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a1, a0, -44
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; RV32I-NEXT: snez a1, a1
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; RV32I-NEXT: addi a0, a0, -92
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; RV32I-NEXT: snez a0, a0
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; RV32I-NEXT: and a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_icmps_const_not1bit_diff:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: addi a1, a0, -44
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; RV64I-NEXT: snez a1, a1
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; RV64I-NEXT: addi a0, a0, -92
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; RV64I-NEXT: snez a0, a0
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; RV64I-NEXT: and a0, a1, a0
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; RV64I-NEXT: ret
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%a = icmp ne i32 %x, 44
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%b = icmp ne i32 %x, 92
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%r = and i1 %a, %b
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ret i1 %r
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}
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