2238dcc393
This is an ongoing series of commits that are reformatting our Python code. Reformatting is done with `black` (23.1.0). If you end up having problems merging this commit because you have made changes to a python file, the best way to handle that is to run `git checkout --ours <yourfile>` and then reformat it with black. RFC: https://discourse.llvm.org/t/rfc-document-and-standardize-python-code-style Differential revision: https://reviews.llvm.org/D151460
83 lines
3.2 KiB
Python
83 lines
3.2 KiB
Python
from lldbsuite.test.lldbtest import *
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from lldbsuite.test.decorators import *
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from lldbsuite.test.gdbclientutils import *
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from textwrap import dedent
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from lldbsuite.test.lldbgdbclient import GDBRemoteTestBase
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class MyResponder(MockGDBServerResponder):
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def qXferRead(self, obj, annex, offset, length):
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if annex == "target.xml":
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return (
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dedent(
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"""\
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<?xml version="1.0"?>
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<target version="1.0">
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<architecture>aarch64</architecture>
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<feature name="org.gnu.gdb.aarch64.core">
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<reg name="x0" bitsize="64"/>
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<reg name="x1" bitsize="64"/>
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<reg name="x2" bitsize="64"/>
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<reg name="x3" bitsize="64"/>
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<reg name="x4" bitsize="64"/>
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<reg name="x5" bitsize="64"/>
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<reg name="x6" bitsize="64"/>
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<reg name="x7" bitsize="64"/>
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<reg name="x8" bitsize="64"/>
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<reg name="x9" bitsize="64"/>
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<reg name="x10" bitsize="64"/>
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<reg name="x11" bitsize="64"/>
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<reg name="x12" bitsize="64"/>
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<reg name="x13" bitsize="64"/>
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<reg name="x14" bitsize="64"/>
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<reg name="x15" bitsize="64"/>
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<reg name="x16" bitsize="64"/>
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<reg name="x17" bitsize="64"/>
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<reg name="x18" bitsize="64"/>
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<reg name="x19" bitsize="64"/>
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<reg name="x20" bitsize="64"/>
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<reg name="x21" bitsize="64"/>
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<reg name="x22" bitsize="64"/>
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<reg name="x23" bitsize="64"/>
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<reg name="x24" bitsize="64"/>
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<reg name="x25" bitsize="64"/>
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<reg name="x26" bitsize="64"/>
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<reg name="x27" bitsize="64"/>
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<reg name="x28" bitsize="64"/>
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<reg name="x29" bitsize="64"/>
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<reg name="x30" bitsize="64"/>
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<reg name="sp" bitsize="64"/>
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<reg name="pc" bitsize="64"/>
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</feature>
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</target>
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"""
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),
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False,
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)
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else:
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return None, False
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class TestQemuAarch64TargetXml(GDBRemoteTestBase):
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@skipIfXmlSupportMissing
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@skipIfRemote
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@skipIfLLVMTargetMissing("AArch64")
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def test_register_augmentation(self):
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"""
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Test that we correctly associate the register info with the eh_frame
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register numbers.
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"""
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target = self.createTarget("basic_eh_frame-aarch64.yaml")
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self.server.responder = MyResponder()
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process = self.connect(target)
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lldbutil.expect_state_changes(
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self, self.dbg.GetListener(), process, [lldb.eStateStopped]
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)
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self.filecheck("image show-unwind -n foo", __file__, "--check-prefix=UNWIND")
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# UNWIND: eh_frame UnwindPlan:
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# UNWIND: row[0]: 0: CFA=x29+16 => x30=[CFA-8]
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