038d884a50
The support is disabled by default. So far there is instruction selection, spilling, and frame elimination. It also changes SP from unswizzled to swizzled as used by flat scratch instructions, so it cannot be mixed with MUBUF stack access. At the very least missing: - GlobalISel; - Some optimizations in frame elimination in between vector and scalar ALU; - It shall finally allow to always materialize frame index as an SGPR, but that is not implemented and frame elimination cannot handle it yet; - Unaligned and/or multidword flat scratch shall work, but it is legalized now for MUBUF; - Operand folding cannot optimize FI like with MUBUF yet; - It will need scaling the value of the SP/FP in the DWARF expression to recover the unswizzled scratch address; Differential Revision: https://reviews.llvm.org/D89170
124 lines
6.0 KiB
LLVM
124 lines
6.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=MUBUF %s
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; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -amdgpu-enable-flat-scratch -verify-machineinstrs | FileCheck -check-prefix=FLATSCR %s
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; FIXME: The MUBUF loads in this test output are incorrect, their SOffset
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; should use the frame offset register, not the ABI stack pointer register. We
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; rely on the frame index argument of MUBUF stack accesses to survive until PEI
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; so we can fix up the SOffset to use the correct frame register in
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; eliminateFrameIndex. Some things like LocalStackSlotAllocation can lift the
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; frame index up into something (e.g. `v_add_nc_u32`) that we cannot fold back
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; into the MUBUF instruction, and so we end up emitting an incorrect offset.
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; Fixing this may involve adding stack access pseudos so that we don't have to
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; speculatively refer to the ABI stack pointer register at all.
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; An assert was hit when frame offset register was used to address FrameIndex.
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define amdgpu_kernel void @kernel_background_evaluate(float addrspace(5)* %kg, <4 x i32> addrspace(1)* %input, <4 x float> addrspace(1)* %output, i32 %i) {
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; MUBUF-LABEL: kernel_background_evaluate:
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; MUBUF: ; %bb.0: ; %entry
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; MUBUF-NEXT: s_load_dword s0, s[0:1], 0x24
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; MUBUF-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
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; MUBUF-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
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; MUBUF-NEXT: s_mov_b32 s38, -1
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; MUBUF-NEXT: s_mov_b32 s39, 0x31c16000
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; MUBUF-NEXT: s_add_u32 s36, s36, s3
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; MUBUF-NEXT: s_addc_u32 s37, s37, 0
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; MUBUF-NEXT: v_mov_b32_e32 v1, 0x2000
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; MUBUF-NEXT: v_mov_b32_e32 v2, 0x4000
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; MUBUF-NEXT: v_mov_b32_e32 v3, 0
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; MUBUF-NEXT: v_mov_b32_e32 v4, 0x400000
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; MUBUF-NEXT: s_mov_b32 s32, 0xc0000
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; MUBUF-NEXT: v_add_nc_u32_e64 v40, 4, 0x4000
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; MUBUF-NEXT: ; implicit-def: $vcc_hi
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; MUBUF-NEXT: s_getpc_b64 s[4:5]
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; MUBUF-NEXT: s_add_u32 s4, s4, svm_eval_nodes@rel32@lo+4
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; MUBUF-NEXT: s_addc_u32 s5, s5, svm_eval_nodes@rel32@hi+12
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; MUBUF-NEXT: s_waitcnt lgkmcnt(0)
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; MUBUF-NEXT: v_mov_b32_e32 v0, s0
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; MUBUF-NEXT: s_mov_b64 s[0:1], s[36:37]
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; MUBUF-NEXT: s_mov_b64 s[2:3], s[38:39]
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; MUBUF-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; MUBUF-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
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; MUBUF-NEXT: s_and_saveexec_b32 s0, vcc_lo
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; MUBUF-NEXT: s_cbranch_execz BB0_2
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; MUBUF-NEXT: ; %bb.1: ; %if.then4.i
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; MUBUF-NEXT: s_clause 0x1
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; MUBUF-NEXT: buffer_load_dword v0, v40, s[36:39], 0 offen
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; MUBUF-NEXT: buffer_load_dword v1, v40, s[36:39], 0 offen offset:4
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; MUBUF-NEXT: s_waitcnt vmcnt(0)
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; MUBUF-NEXT: v_add_nc_u32_e32 v0, v1, v0
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; MUBUF-NEXT: v_mul_lo_u32 v0, 0x41c64e6d, v0
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; MUBUF-NEXT: v_add_nc_u32_e32 v0, 0x3039, v0
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; MUBUF-NEXT: buffer_store_dword v0, v0, s[36:39], 0 offen
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; MUBUF-NEXT: BB0_2: ; %shader_eval_surface.exit
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; MUBUF-NEXT: s_endpgm
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;
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; FLATSCR-LABEL: kernel_background_evaluate:
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; FLATSCR: ; %bb.0: ; %entry
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; FLATSCR-NEXT: s_add_u32 s2, s2, s5
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; FLATSCR-NEXT: s_movk_i32 s32, 0x6000
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; FLATSCR-NEXT: s_addc_u32 s3, s3, 0
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; FLATSCR-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
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; FLATSCR-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
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; FLATSCR-NEXT: s_load_dword s0, s[0:1], 0x24
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; FLATSCR-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
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; FLATSCR-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
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; FLATSCR-NEXT: s_mov_b32 s38, -1
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; FLATSCR-NEXT: s_mov_b32 s39, 0x31c16000
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; FLATSCR-NEXT: s_add_u32 s36, s36, s5
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; FLATSCR-NEXT: s_addc_u32 s37, s37, 0
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; FLATSCR-NEXT: v_mov_b32_e32 v1, 0x2000
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; FLATSCR-NEXT: v_mov_b32_e32 v2, 0x4000
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; FLATSCR-NEXT: v_mov_b32_e32 v3, 0
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; FLATSCR-NEXT: v_mov_b32_e32 v4, 0x400000
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; FLATSCR-NEXT: ; implicit-def: $vcc_hi
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; FLATSCR-NEXT: s_getpc_b64 s[4:5]
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; FLATSCR-NEXT: s_add_u32 s4, s4, svm_eval_nodes@rel32@lo+4
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; FLATSCR-NEXT: s_addc_u32 s5, s5, svm_eval_nodes@rel32@hi+12
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; FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
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; FLATSCR-NEXT: v_mov_b32_e32 v0, s0
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; FLATSCR-NEXT: s_mov_b64 s[0:1], s[36:37]
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; FLATSCR-NEXT: s_mov_b64 s[2:3], s[38:39]
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; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; FLATSCR-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
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; FLATSCR-NEXT: s_and_saveexec_b32 s0, vcc_lo
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; FLATSCR-NEXT: s_cbranch_execz BB0_2
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; FLATSCR-NEXT: ; %bb.1: ; %if.then4.i
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; FLATSCR-NEXT: s_movk_i32 vcc_lo, 0x4000
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; FLATSCR-NEXT: s_nop 1
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; FLATSCR-NEXT: scratch_load_dword v0, off, vcc_lo offset:4
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; FLATSCR-NEXT: s_waitcnt_depctr 0xffe3
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; FLATSCR-NEXT: s_movk_i32 vcc_lo, 0x4000
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; FLATSCR-NEXT: scratch_load_dword v1, off, vcc_lo offset:8
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; FLATSCR-NEXT: s_waitcnt vmcnt(0)
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; FLATSCR-NEXT: v_add_nc_u32_e32 v0, v1, v0
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; FLATSCR-NEXT: v_mul_lo_u32 v0, 0x41c64e6d, v0
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; FLATSCR-NEXT: v_add_nc_u32_e32 v0, 0x3039, v0
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; FLATSCR-NEXT: scratch_store_dword off, v0, s0
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; FLATSCR-NEXT: BB0_2: ; %shader_eval_surface.exit
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; FLATSCR-NEXT: s_endpgm
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entry:
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%sd = alloca < 1339 x i32>, align 8192, addrspace(5)
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%state = alloca <4 x i32>, align 16, addrspace(5)
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%rslt = call i32 @svm_eval_nodes(float addrspace(5)* %kg, <1339 x i32> addrspace(5)* %sd, <4 x i32> addrspace(5)* %state, i32 0, i32 4194304)
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%cmp = icmp eq i32 %rslt, 0
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br i1 %cmp, label %shader_eval_surface.exit, label %if.then4.i
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if.then4.i: ; preds = %entry
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%rng_hash.i.i = getelementptr inbounds < 4 x i32>, <4 x i32> addrspace(5)* %state, i32 0, i32 1
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%tmp0 = load i32, i32 addrspace(5)* %rng_hash.i.i, align 4
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%rng_offset.i.i = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %state, i32 0, i32 2
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%tmp1 = load i32, i32 addrspace(5)* %rng_offset.i.i, align 4
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%add.i.i = add i32 %tmp1, %tmp0
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%add1.i.i = add i32 %add.i.i, 0
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%mul.i.i.i.i = mul i32 %add1.i.i, 1103515245
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%add.i.i.i.i = add i32 %mul.i.i.i.i, 12345
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store i32 %add.i.i.i.i, i32 addrspace(5)* undef, align 16
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br label %shader_eval_surface.exit
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shader_eval_surface.exit: ; preds = %entry
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ret void
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}
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declare hidden i32 @svm_eval_nodes(float addrspace(5)*, <1339 x i32> addrspace(5)*, <4 x i32> addrspace(5)*, i32, i32) local_unnamed_addr
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