a3cefa5d64
This patch follows some ideas from r352866 to optimize the floating point materialization even further. It changes isFPImmLegal to considere up to 2 mov instruction or up to 5 in case subtarget has fused literals. The rationale is the cost is the same for mov+fmov vs. adrp+ldr; but the mov+fmov sequence is always better because of the reduced d-cache pressure. The timings are still the same if you consider movw+movk+fmov vs. adrp+ldr will be fused (although one instruction longer). Reviewers: efriedma Differential Revision: https://reviews.llvm.org/D58460 llvm-svn: 356390
25 lines
944 B
LLVM
25 lines
944 B
LLVM
; RUN: llc < %s -mtriple=aarch64-win32-msvc | FileCheck %s
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; RUN: llc < %s -mtriple=aarch64-win32-gnu | FileCheck -check-prefix=MINGW %s
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define double @double() {
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ret double 0x2000000000800001
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}
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; CHECK: .globl __real@2000000000800001
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; CHECK-NEXT: .section .rdata,"dr",discard,__real@2000000000800001
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; CHECK-NEXT: .p2align 3
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; CHECK-NEXT: __real@2000000000800001:
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; CHECK-NEXT: .xword 2305843009222082561
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; CHECK: double:
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; CHECK: adrp x8, __real@2000000000800001
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; CHECK-NEXT: ldr d0, [x8, __real@2000000000800001]
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; CHECK-NEXT: ret
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; MINGW: .section .rdata,"dr"
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; MINGW-NEXT: .p2align 3
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; MINGW-NEXT: [[LABEL:\.LC.*]]:
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; MINGW-NEXT: .xword 2305843009222082561
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; MINGW: double:
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; MINGW: adrp x8, [[LABEL]]
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; MINGW-NEXT: ldr d0, [x8, [[LABEL]]]
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; MINGW-NEXT: ret
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