fdd761af15
Mostsly these would fail due to trying to use SI with a flat operation. Implementing global loads with MUBUF is more work than flat, so these won't be handled in the initial load selection. Others fail because store of s64 won't initially work, as the current set of patterns expect everything to be turned into v2i32. llvm-svn: 365493
71 lines
3.3 KiB
YAML
71 lines
3.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
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---
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name: sub_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
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; GFX6-LABEL: name: sub_s32
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; GFX6: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
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; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[S_SUB_U32_:%[0-9]+]]:sreg_32_xm0 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
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; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_SUB_I32_e64 [[COPY2]], [[S_SUB_U32_]], 0, implicit $exec
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; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_SUB_I32_e64 [[S_SUB_U32_]], %7, 0, implicit $exec
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; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_SUB_I32_e64 %8, [[COPY2]], 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit %9
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; GFX9-LABEL: name: sub_s32
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; GFX9: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[S_SUB_U32_:%[0-9]+]]:sreg_32_xm0 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
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; GFX9: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY2]], [[S_SUB_U32_]], 0, implicit $exec
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; GFX9: [[V_SUB_U32_e64_1:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[S_SUB_U32_]], [[V_SUB_U32_e64_]], 0, implicit $exec
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; GFX9: [[V_SUB_U32_e64_2:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[V_SUB_U32_e64_1]], [[COPY2]], 0, implicit $exec
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; GFX9: S_ENDPGM 0, implicit [[V_SUB_U32_e64_2]]
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; GFX10-LABEL: name: sub_s32
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; GFX10: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
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; GFX10: $vcc_hi = IMPLICIT_DEF
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; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX10: [[S_SUB_U32_:%[0-9]+]]:sreg_32_xm0 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
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; GFX10: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY2]], [[S_SUB_U32_]], 0, implicit $exec
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; GFX10: [[V_SUB_U32_e64_1:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[S_SUB_U32_]], [[V_SUB_U32_e64_]], 0, implicit $exec
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; GFX10: [[V_SUB_U32_e64_2:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[V_SUB_U32_e64_1]], [[COPY2]], 0, implicit $exec
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; GFX10: S_ENDPGM 0, implicit [[V_SUB_U32_e64_2]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:vgpr(s32) = COPY $vgpr0
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%3:vgpr(p1) = COPY $vgpr3_vgpr4
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%4:sgpr(s32) = G_CONSTANT i32 1
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%5:sgpr(s32) = G_CONSTANT i32 4096
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; sub ss
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%6:sgpr(s32) = G_SUB %0, %1
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; sub vs
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%7:vgpr(s32) = G_SUB %2, %6
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; sub sv
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%8:vgpr(s32) = G_SUB %6, %7
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; sub vv
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%9:vgpr(s32) = G_SUB %8, %2
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S_ENDPGM 0, implicit %9
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...
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