71dfb7ec5c
Make the FP register callee saved. This is tricky because now the FP needs to be spilled in the prolog relative to the incoming SP register, rather than the frame register used throughout the rest of the function. I don't like how this bypassess the standard mechanism for CSR spills just to get the correct insert point. I may look for a better solution, since all CSR VGPRs may also need to have all lanes activated. Another option might be to make getFrameIndexReference change the base register if the frame index is a CSR, and then try to figure out the right insertion point in emitProlog. If there is a free VGPR lane available for SGPR spilling, try to use it for the FP. If that would require intrtoducing a new VGPR spill, try to use a free call clobbered SGPR. Only fallback to introducing a new VGPR spill as a last resort. This also doesn't attempt to handle SGPR spilling with scalar stores. llvm-svn: 365372
88 lines
3.4 KiB
LLVM
88 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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define i32 @atomic_nand_i32_lds(i32 addrspace(3)* %ptr) nounwind {
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; GCN-LABEL: atomic_nand_i32_lds:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: ds_read_b32 v2, v0
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; GCN-NEXT: s_mov_b64 s[4:5], 0
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; GCN-NEXT: BB0_1: ; %atomicrmw.start
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_not_b32_e32 v1, v2
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; GCN-NEXT: v_or_b32_e32 v1, -5, v1
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; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GCN-NEXT: ds_cmpst_rtn_b32 v1, v0, v2, v1
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; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GCN-NEXT: buffer_wbinvl1_vol
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; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
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; GCN-NEXT: v_mov_b32_e32 v2, v1
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; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
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; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5]
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; GCN-NEXT: s_cbranch_execnz BB0_1
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; GCN-NEXT: ; %bb.2: ; %atomicrmw.end
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; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
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; GCN-NEXT: v_mov_b32_e32 v0, v1
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%result = atomicrmw nand i32 addrspace(3)* %ptr, i32 4 seq_cst
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ret i32 %result
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}
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define i32 @atomic_nand_i32_global(i32 addrspace(1)* %ptr) nounwind {
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; GCN-LABEL: atomic_nand_i32_global:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: global_load_dword v3, v[0:1], off
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; GCN-NEXT: s_mov_b64 s[4:5], 0
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; GCN-NEXT: BB1_1: ; %atomicrmw.start
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_not_b32_e32 v2, v3
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; GCN-NEXT: v_or_b32_e32 v2, -5, v2
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; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GCN-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc
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; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GCN-NEXT: buffer_wbinvl1_vol
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; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
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; GCN-NEXT: v_mov_b32_e32 v3, v2
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; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
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; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5]
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; GCN-NEXT: s_cbranch_execnz BB1_1
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; GCN-NEXT: ; %bb.2: ; %atomicrmw.end
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; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
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; GCN-NEXT: v_mov_b32_e32 v0, v2
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%result = atomicrmw nand i32 addrspace(1)* %ptr, i32 4 seq_cst
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ret i32 %result
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}
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define i32 @atomic_nand_i32_flat(i32* %ptr) nounwind {
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; GCN-LABEL: atomic_nand_i32_flat:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: flat_load_dword v3, v[0:1]
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; GCN-NEXT: s_mov_b64 s[4:5], 0
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; GCN-NEXT: BB2_1: ; %atomicrmw.start
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_not_b32_e32 v2, v3
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; GCN-NEXT: v_or_b32_e32 v2, -5, v2
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; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GCN-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
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; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GCN-NEXT: buffer_wbinvl1_vol
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
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; GCN-NEXT: v_mov_b32_e32 v3, v2
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; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
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; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5]
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; GCN-NEXT: s_cbranch_execnz BB2_1
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; GCN-NEXT: ; %bb.2: ; %atomicrmw.end
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; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
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; GCN-NEXT: v_mov_b32_e32 v0, v2
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%result = atomicrmw nand i32* %ptr, i32 4 seq_cst
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ret i32 %result
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}
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