b3438f1cc0
As we perform a zext on any arguments used in the promoted tree, it doesn't matter if they're marked as signext. The only permitted user(s) in the tree which would interpret the sign bits are signed icmps. For these instructions, their promoted operands are truncated before the icmp uses them. Differential Revision: https://reviews.llvm.org/D68019 llvm-svn: 373186
90 lines
2.5 KiB
LLVM
90 lines
2.5 KiB
LLVM
; RUN: llc -mtriple=thumbv7em -arm-disable-cgp=false %s -o - | FileCheck %s
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; RUN: llc -mtriple=thumbv8m.main -mattr=+dsp -arm-disable-cgp=false %s -o - | FileCheck %s
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; RUN: llc -mtriple=thumbv7 %s -arm-disable-cgp=false -o - | FileCheck %s
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; RUN: llc -mtriple=armv8 %s -arm-disable-cgp=false -o - | FileCheck %s
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; Test to check that ARMCodeGenPrepare doesn't optimised away sign extends.
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; CHECK-LABEL: test_signed_load:
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; CHECK: uxth
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define i16 @test_signed_load(i16* %ptr) {
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%load = load i16, i16* %ptr
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%conv0 = zext i16 %load to i32
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%conv1 = sext i16 %load to i32
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%cmp = icmp eq i32 %conv0, %conv1
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%conv2 = zext i1 %cmp to i16
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ret i16 %conv2
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}
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; Don't allow sign bit generating opcodes.
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; CHECK-LABEL: test_ashr:
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; CHECK: sxth
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define i16 @test_ashr(i16 zeroext %arg) {
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%ashr = ashr i16 %arg, 1
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%cmp = icmp eq i16 %ashr, 0
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%conv = zext i1 %cmp to i16
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ret i16 %conv
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}
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; CHECK-LABEL: test_sdiv:
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; CHECK: sxth
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define i16 @test_sdiv(i16 zeroext %arg) {
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%sdiv = sdiv i16 %arg, 2
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%cmp = icmp ne i16 %sdiv, 0
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%conv = zext i1 %cmp to i16
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ret i16 %conv
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}
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; CHECK-LABEL: test_srem
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; CHECK: sxth
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define i16 @test_srem(i16 zeroext %arg) {
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%srem = srem i16 %arg, 4
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%cmp = icmp ne i16 %srem, 0
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%conv = zext i1 %cmp to i16
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ret i16 %conv
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}
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; CHECK-LABEL: test_signext_b
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; CHECK: ldrb [[LDR:r[0-9]+]], [r0]
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; CHECK: uxtab [[UXT:r[0-9]+]], [[LDR]], r1
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; CHECK: cm{{.*}} [[UXT]], #128
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define i32 @test_signext_b(i8* %ptr, i8 signext %arg) {
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entry:
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%0 = load i8, i8* %ptr, align 1
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%1 = add nuw nsw i8 %0, %arg
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%cmp = icmp ult i8 %1, 128
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%res = select i1 %cmp, i32 42, i32 20894
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ret i32 %res
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}
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; CHECK-LABEL: test_signext_b_ult_slt
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; CHECK: ldrb [[LDR:r[0-9]+]], [r0]
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; CHECK: uxtab [[ADD:r[0-9]+]], [[LDR]], r1
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; CHECK: uxtb [[UXT:r[0-9]+]], r1
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; CHECK: cmp [[ADD]], [[UXT]]
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; CHECK: uxtb [[TRUNC:r[0-9]+]], [[ADD]]
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; CHECK: cmp [[TRUNC]], #127
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define i32 @test_signext_b_ult_slt(i8* %ptr, i8 signext %arg) {
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entry:
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%0 = load i8, i8* %ptr, align 1
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%1 = add nuw nsw i8 %0, %arg
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%cmp = icmp sle i8 %1, 126
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%cmp.1 = icmp ule i8 %1, %arg
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%or = and i1 %cmp, %cmp.1
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%res = select i1 %or, i32 42, i32 57
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ret i32 %res
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}
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; CHECK-LABEL: test_signext_h
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; CHECK: ldrh [[LDR:r[0-9]+]], [r0]
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; CHECK: uxtah [[ADD:r[0-9]+]], [[LDR]], r1
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; CHECK: cm{{.*}} [[ADD]],
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define i32 @test_signext_h(i16* %ptr, i16 signext %arg) {
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entry:
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%0 = load i16, i16* %ptr, align 1
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%1 = add nuw nsw i16 %0, %arg
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%cmp = icmp ult i16 %1, 32768
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%res = select i1 %cmp, i32 42, i32 20894
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ret i32 %res
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}
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