b6e83b98f9
Make it possible to TableGen code for FCONSTS and FCONSTD. We need to make two changes to the TableGen descriptions of vfp_f32imm and vfp_f64imm respectively: * add GISelPredicateCode to check that the immediate fits in 8 bits; * extract the SDNodeXForms into separate definitions and create a GISDNodeXFormEquiv and a custom renderer function for each of them. There's a lot of boilerplate to get the actual value of the immediate, but it basically just boils down to calling ARM_AM::getFP32Imm or ARM_AM::getFP64Imm. llvm-svn: 358063
140 lines
4.0 KiB
YAML
140 lines
4.0 KiB
YAML
# RUN: llc -O0 -mtriple arm-- -mattr=+vfp3,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP3
|
|
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+vfp3,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP3
|
|
# RUN: llc -O0 -mtriple arm-- -mattr=+vfp2,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP2
|
|
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+vfp2,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP2
|
|
--- |
|
|
define void @test_fpconst_zero_s32() { ret void }
|
|
define void @test_fpconst_zero_s64() { ret void }
|
|
|
|
define void @test_fpconst_8bit_s32() { ret void }
|
|
define void @test_fpconst_8bit_s64() { ret void }
|
|
...
|
|
---
|
|
name: test_fpconst_zero_s32
|
|
# CHECK-LABEL: name: test_fpconst_zero_s32
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: fprb }
|
|
# CHECK: constants:
|
|
# CHECK-NEXT: id: 0
|
|
# CHECK-NEXT: value: 'float 0.000000e+00'
|
|
# CHECK-NEXT: alignment: 4
|
|
# CHECK-NEXT: isTargetSpecific: false
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0
|
|
|
|
%0(p0) = COPY $r0
|
|
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
|
|
|
|
%1(s32) = G_FCONSTANT float 0.0
|
|
; CHECK: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
|
|
|
|
G_STORE %1(s32), %0 :: (store 4)
|
|
; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14, $noreg
|
|
|
|
BX_RET 14, $noreg
|
|
; CHECK: BX_RET 14, $noreg
|
|
...
|
|
---
|
|
name: test_fpconst_zero_s64
|
|
# CHECK-LABEL: name: test_fpconst_zero_s64
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: fprb }
|
|
# CHECK: constants:
|
|
# CHECK-NEXT: id: 0
|
|
# CHECK-NEXT: value: 'double 0.000000e+00'
|
|
# CHECK-NEXT: alignment: 8
|
|
# CHECK-NEXT: isTargetSpecific: false
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0
|
|
|
|
%0(p0) = COPY $r0
|
|
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
|
|
|
|
%1(s64) = G_FCONSTANT double 0.0
|
|
; CHECK: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14, $noreg :: (load 8 from constant-pool)
|
|
|
|
G_STORE %1(s64), %0 :: (store 8)
|
|
; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14, $noreg
|
|
|
|
BX_RET 14, $noreg
|
|
; CHECK: BX_RET 14, $noreg
|
|
...
|
|
---
|
|
name: test_fpconst_8bit_s32
|
|
# CHECK-LABEL: name: test_fpconst_8bit_s32
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: fprb }
|
|
# VFP3: constants: []
|
|
# VFP2: constants:
|
|
# VFP2-NEXT: id: 0
|
|
# VFP2-NEXT: value: 'float -2.000000e+00'
|
|
# VFP2-NEXT: alignment: 4
|
|
# VFP2-NEXT: isTargetSpecific: false
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0
|
|
|
|
%0(p0) = COPY $r0
|
|
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
|
|
|
|
%1(s32) = G_FCONSTANT float -2.0
|
|
; VFP3: [[VREG:%[0-9]+]]:spr = FCONSTS 128, 14, $noreg
|
|
; VFP2: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
|
|
|
|
G_STORE %1(s32), %0 :: (store 4)
|
|
; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14, $noreg
|
|
|
|
BX_RET 14, $noreg
|
|
; CHECK: BX_RET 14, $noreg
|
|
...
|
|
---
|
|
name: test_fpconst_8bit_s64
|
|
# CHECK-LABEL: name: test_fpconst_8bit_s64
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: fprb }
|
|
# VFP3: constants: []
|
|
# VFP2: constants:
|
|
# VFP2-NEXT: id: 0
|
|
# VFP2-NEXT: value: double 5.000000e-01
|
|
# VFP2-NEXT: alignment: 8
|
|
# VFP2-NEXT: isTargetSpecific: false
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0
|
|
|
|
%0(p0) = COPY $r0
|
|
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
|
|
|
|
%1(s64) = G_FCONSTANT double 5.0e-1
|
|
; VFP3: [[VREG:%[0-9]+]]:dpr = FCONSTD 96, 14, $noreg
|
|
; VFP2: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14, $noreg :: (load 8 from constant-pool)
|
|
|
|
G_STORE %1(s64), %0 :: (store 8)
|
|
; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14, $noreg
|
|
|
|
BX_RET 14, $noreg
|
|
; CHECK: BX_RET 14, $noreg
|
|
...
|