b6c7fce67a
Reapply with fix to reduce resources required by the compiler - use unsigned[2] instead of std::pair. This causes clang and gcc to compile the generated file multiple times faster, and hopefully will reduce the resource requirements on Visual Studio also. This fix is a little ugly but it's clearly the same issue the previous author of DFAPacketizer faced (the previous tables use unsigned[2] rather uglily too). This patch allows the DFAPacketizer to be queried after a packet is formed to work out which resources were allocated to the packetized instructions. This is particularly important for targets that do their own bundle packing - it's not sufficient to know simply that instructions can share a packet; which slots are used is also required for encoding. This extends the emitter to emit a side-table containing resource usage diffs for each state transition. The packetizer maintains a set of all possible resource states in its current state. After packetization is complete, all remaining resource states are possible packetization strategies. The sidetable is only ~500K for Hexagon, but the extra tracking is disabled by default (most uses of the packetizer like MachinePipeliner don't care and don't need the extra maintained state). Differential Revision: https://reviews.llvm.org/D66936 llvm-svn: 371399
30 lines
837 B
LLVM
30 lines
837 B
LLVM
; RUN: llc -O2 -march=hexagon < %s -debug-only=packets 2>&1 | FileCheck %s
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; REQUIRES: asserts
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; CHECK: Finalizing packet:
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; CHECK-NEXT: * [res:0x8] renamable $r1 = S2_vsplatrb renamable $r0
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; CHECK-NEXT: * [res:0x4] renamable $d1 = S2_vsplatrh killed renamable $r0
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target triple = "hexagon"
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; Function Attrs: nounwind readnone
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define i64 @f0(i64 %a0) #0 {
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b0:
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%v0 = trunc i64 %a0 to i32
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%v1 = and i32 %v0, 65535
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%v2 = tail call i64 @llvm.hexagon.S2.vsplatrh(i32 %v1)
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%v3 = and i32 %v0, 255
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%v4 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %v3)
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%v5 = sext i32 %v4 to i64
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%v6 = add nsw i64 %v5, %v2
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ret i64 %v6
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}
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.S2.vsplatrh(i32) #0
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.S2.vsplatrb(i32) #0
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attributes #0 = { nounwind readnone }
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