caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
7653ff398d28851b211e81fa6ab22dd94de16f92
clang-p2996/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir
Guillaume Chatelet 48904e9452 [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,

This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67433

llvm-svn: 371608
2019-09-11 11:16:48 +00:00

181 lines
6.9 KiB
YAML
Raw Blame History

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP64
--- |
define void @select_i32() {entry: ret void}
define void @select_ptr() {entry: ret void}
define void @select_float() {entry: ret void}
define void @select_double() {entry: ret void}
...
---
name: select_i32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; MIPS32FP32-LABEL: name: select_i32
; MIPS32FP32: liveins: $a0, $a1, $a2
; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
; MIPS32FP32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
; MIPS32FP32: $v0 = COPY [[MOVN_I_I]]
; MIPS32FP32: RetRA implicit $v0
; MIPS32FP64-LABEL: name: select_i32
; MIPS32FP64: liveins: $a0, $a1, $a2
; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
; MIPS32FP64: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
; MIPS32FP64: $v0 = COPY [[MOVN_I_I]]
; MIPS32FP64: RetRA implicit $v0
%3:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = COPY $a2
%6:gprb(s32) = G_CONSTANT i32 1
%7:gprb(s32) = COPY %3(s32)
%5:gprb(s32) = G_AND %7, %6
%4:gprb(s32) = G_SELECT %5(s32), %1, %2
$v0 = COPY %4(s32)
RetRA implicit $v0
...
---
name: select_ptr
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; MIPS32FP32-LABEL: name: select_ptr
; MIPS32FP32: liveins: $a0, $a1, $a2
; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
; MIPS32FP32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
; MIPS32FP32: $v0 = COPY [[MOVN_I_I]]
; MIPS32FP32: RetRA implicit $v0
; MIPS32FP64-LABEL: name: select_ptr
; MIPS32FP64: liveins: $a0, $a1, $a2
; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
; MIPS32FP64: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
; MIPS32FP64: $v0 = COPY [[MOVN_I_I]]
; MIPS32FP64: RetRA implicit $v0
%3:gprb(s32) = COPY $a0
%1:gprb(p0) = COPY $a1
%2:gprb(p0) = COPY $a2
%6:gprb(s32) = G_CONSTANT i32 1
%7:gprb(s32) = COPY %3(s32)
%5:gprb(s32) = G_AND %7, %6
%4:gprb(p0) = G_SELECT %5(s32), %1, %2
$v0 = COPY %4(p0)
RetRA implicit $v0
...
---
name: select_float
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; MIPS32FP32-LABEL: name: select_float
; MIPS32FP32: liveins: $a0, $a1, $a2
; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32FP32: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1
; MIPS32FP32: [[MTC1_1:%[0-9]+]]:fgr32 = MTC1 $a2
; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
; MIPS32FP32: [[MOVN_I_S:%[0-9]+]]:fgr32 = MOVN_I_S [[MTC1_]], [[AND]], [[MTC1_1]]
; MIPS32FP32: $f0 = COPY [[MOVN_I_S]]
; MIPS32FP32: RetRA implicit $f0
; MIPS32FP64-LABEL: name: select_float
; MIPS32FP64: liveins: $a0, $a1, $a2
; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32FP64: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1
; MIPS32FP64: [[MTC1_1:%[0-9]+]]:fgr32 = MTC1 $a2
; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
; MIPS32FP64: [[MOVN_I_S:%[0-9]+]]:fgr32 = MOVN_I_S [[MTC1_]], [[AND]], [[MTC1_1]]
; MIPS32FP64: $f0 = COPY [[MOVN_I_S]]
; MIPS32FP64: RetRA implicit $f0
%3:gprb(s32) = COPY $a0
%1:fgr32(s32) = MTC1 $a1
%2:fgr32(s32) = MTC1 $a2
%6:gprb(s32) = G_CONSTANT i32 1
%7:gprb(s32) = COPY %3(s32)
%5:gprb(s32) = G_AND %7, %6
%4:fprb(s32) = G_SELECT %5(s32), %1, %2
$f0 = COPY %4(s32)
RetRA implicit $f0
...
---
name: select_double
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
fixedStack:
- { id: 0, offset: 16, size: 4, alignment: 8, isImmutable: true }
body: |
bb.1.entry:
liveins: $d6, $d7
; MIPS32FP32-LABEL: name: select_double
; MIPS32FP32: liveins: $d6, $d7
; MIPS32FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; MIPS32FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
; MIPS32FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
; MIPS32FP32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[LW]], [[ORi]]
; MIPS32FP32: [[MOVN_I_D32_:%[0-9]+]]:afgr64 = MOVN_I_D32 [[COPY]], [[AND]], [[COPY1]]
; MIPS32FP32: $d0 = COPY [[MOVN_I_D32_]]
; MIPS32FP32: RetRA implicit $d0
; MIPS32FP64-LABEL: name: select_double
; MIPS32FP64: liveins: $d6, $d7
; MIPS32FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; MIPS32FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
; MIPS32FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
; MIPS32FP64: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[LW]], [[ORi]]
; MIPS32FP64: [[MOVN_I_D64_:%[0-9]+]]:fgr64 = MOVN_I_D64 [[COPY]], [[AND]], [[COPY1]]
; MIPS32FP64: $d0 = COPY [[MOVN_I_D64_]]
; MIPS32FP64: RetRA implicit $d0
%0:fprb(s64) = COPY $d6
%1:fprb(s64) = COPY $d7
%4:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
%3:gprb(s32) = G_LOAD %4(p0) :: (load 4 from %fixed-stack.0, align 8)
%7:gprb(s32) = G_CONSTANT i32 1
%8:gprb(s32) = COPY %3(s32)
%6:gprb(s32) = G_AND %8, %7
%5:fprb(s64) = G_SELECT %6(s32), %0, %1
$d0 = COPY %5(s64)
RetRA implicit $d0
...
Reference in New Issue View Git Blame Copy Permalink