828b685ebe
Trace through multiple COPYs when looking for a physreg source. Add hinting for vregs that will be copied into physregs (we only hinted for vregs getting copied to a physreg previously). Give hinted a register a bonus when deciding which value to spill. This is part of my rewrite regallocfast series. In fact this one doesn't even have an effect unless you also flip the allocation to happen from back to front of a basic block. Nonetheless it helps to split this up to ease review of D52010 Patch by Matthias Braun llvm-svn: 360887
171 lines
6.0 KiB
LLVM
171 lines
6.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -fast-isel-sink-local-values -O0 -mtriple=x86_64-unknown-linux-gnu -o - %s | FileCheck %s -check-prefix=X640
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; RUN: llc -fast-isel-sink-local-values -O0 -mtriple=i686-unknown -o - %s | FileCheck %s -check-prefix=6860
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; RUN: llc -fast-isel-sink-local-values -mtriple=x86_64-unknown-linux-gnu -o - %s | FileCheck %s -check-prefix=X64
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; RUN: llc -fast-isel-sink-local-values -mtriple=i686-unknown -o - %s | FileCheck %s -check-prefix=686
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@var_22 = external global i16, align 2
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@var_27 = external global i16, align 2
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define void @foo() {
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; X640-LABEL: foo:
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; X640: # %bb.0: # %bb
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; X640-NEXT: movzwl var_22, %eax
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; X640-NEXT: movzwl var_27, %ecx
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; X640-NEXT: xorl %ecx, %eax
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; X640-NEXT: movzwl var_27, %ecx
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; X640-NEXT: xorl %ecx, %eax
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; X640-NEXT: movslq %eax, %rdx
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; X640-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
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; X640-NEXT: movzwl var_22, %eax
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; X640-NEXT: movzwl var_27, %ecx
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; X640-NEXT: xorl %ecx, %eax
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; X640-NEXT: movzwl var_27, %ecx
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; X640-NEXT: xorl %ecx, %eax
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; X640-NEXT: movslq %eax, %rdx
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; X640-NEXT: movzwl var_27, %eax
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; X640-NEXT: subl $16610, %eax # imm = 0x40E2
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; X640-NEXT: movl %eax, %eax
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; X640-NEXT: movl %eax, %ecx
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; X640-NEXT: # kill: def $cl killed $rcx
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; X640-NEXT: sarq %cl, %rdx
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; X640-NEXT: # kill: def $dl killed $dl killed $rdx
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; X640-NEXT: # implicit-def: $rsi
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; X640-NEXT: movb %dl, (%rsi)
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; X640-NEXT: retq
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;
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; 6860-LABEL: foo:
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; 6860: # %bb.0: # %bb
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; 6860-NEXT: pushl %ebp
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; 6860-NEXT: .cfi_def_cfa_offset 8
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; 6860-NEXT: .cfi_offset %ebp, -8
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; 6860-NEXT: movl %esp, %ebp
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; 6860-NEXT: .cfi_def_cfa_register %ebp
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; 6860-NEXT: pushl %ebx
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; 6860-NEXT: pushl %edi
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; 6860-NEXT: pushl %esi
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; 6860-NEXT: andl $-8, %esp
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; 6860-NEXT: subl $32, %esp
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; 6860-NEXT: .cfi_offset %esi, -20
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; 6860-NEXT: .cfi_offset %edi, -16
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; 6860-NEXT: .cfi_offset %ebx, -12
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; 6860-NEXT: movw var_22, %ax
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; 6860-NEXT: movzwl var_27, %ecx
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; 6860-NEXT: movw %cx, %dx
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; 6860-NEXT: xorw %dx, %ax
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; 6860-NEXT: # implicit-def: $esi
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; 6860-NEXT: movw %ax, %si
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; 6860-NEXT: xorl %ecx, %esi
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; 6860-NEXT: # kill: def $si killed $si killed $esi
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; 6860-NEXT: movzwl %si, %ecx
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; 6860-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; 6860-NEXT: movl $0, {{[0-9]+}}(%esp)
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; 6860-NEXT: movw var_22, %ax
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; 6860-NEXT: movzwl var_27, %ecx
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; 6860-NEXT: movw %cx, %dx
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; 6860-NEXT: xorw %dx, %ax
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; 6860-NEXT: # implicit-def: $edi
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; 6860-NEXT: movw %ax, %di
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; 6860-NEXT: xorl %ecx, %edi
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; 6860-NEXT: # kill: def $di killed $di killed $edi
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; 6860-NEXT: movzwl %di, %ebx
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; 6860-NEXT: # kill: def $cl killed $cl killed $ecx
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; 6860-NEXT: addb $30, %cl
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; 6860-NEXT: xorl %eax, %eax
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; 6860-NEXT: movb %cl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
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; 6860-NEXT: shrdl %cl, %eax, %ebx
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; 6860-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %cl # 1-byte Reload
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; 6860-NEXT: testb $32, %cl
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; 6860-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
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; 6860-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
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; 6860-NEXT: jne .LBB0_2
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; 6860-NEXT: # %bb.1: # %bb
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; 6860-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
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; 6860-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
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; 6860-NEXT: .LBB0_2: # %bb
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; 6860-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
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; 6860-NEXT: # kill: def $al killed $al killed $eax
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; 6860-NEXT: # implicit-def: $ecx
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; 6860-NEXT: movb %al, (%ecx)
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; 6860-NEXT: leal -12(%ebp), %esp
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; 6860-NEXT: popl %esi
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; 6860-NEXT: popl %edi
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; 6860-NEXT: popl %ebx
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; 6860-NEXT: popl %ebp
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; 6860-NEXT: .cfi_def_cfa %esp, 4
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; 6860-NEXT: retl
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;
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; X64-LABEL: foo:
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; X64: # %bb.0: # %bb
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; X64-NEXT: movzwl {{.*}}(%rip), %ecx
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; X64-NEXT: movzwl {{.*}}(%rip), %eax
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; X64-NEXT: xorw %cx, %ax
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; X64-NEXT: xorl %ecx, %eax
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; X64-NEXT: movzwl %ax, %eax
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; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
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; X64-NEXT: addb $30, %cl
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; X64-NEXT: # kill: def $cl killed $cl killed $ecx
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; X64-NEXT: shrq %cl, %rax
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; X64-NEXT: movb %al, (%rax)
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; X64-NEXT: retq
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;
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; 686-LABEL: foo:
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; 686: # %bb.0: # %bb
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; 686-NEXT: pushl %ebp
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; 686-NEXT: .cfi_def_cfa_offset 8
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; 686-NEXT: .cfi_offset %ebp, -8
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; 686-NEXT: movl %esp, %ebp
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; 686-NEXT: .cfi_def_cfa_register %ebp
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; 686-NEXT: andl $-8, %esp
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; 686-NEXT: subl $8, %esp
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; 686-NEXT: movzwl var_27, %ecx
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; 686-NEXT: movzwl var_22, %eax
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; 686-NEXT: xorw %cx, %ax
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; 686-NEXT: xorl %ecx, %eax
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; 686-NEXT: movzwl %ax, %eax
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; 686-NEXT: movl %eax, (%esp)
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; 686-NEXT: movl $0, {{[0-9]+}}(%esp)
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; 686-NEXT: addb $30, %cl
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; 686-NEXT: xorl %edx, %edx
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; 686-NEXT: shrdl %cl, %edx, %eax
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; 686-NEXT: testb $32, %cl
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; 686-NEXT: jne .LBB0_2
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; 686-NEXT: # %bb.1: # %bb
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; 686-NEXT: movl %eax, %edx
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; 686-NEXT: .LBB0_2: # %bb
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; 686-NEXT: movb %dl, (%eax)
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; 686-NEXT: movl %ebp, %esp
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; 686-NEXT: popl %ebp
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; 686-NEXT: .cfi_def_cfa %esp, 4
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; 686-NEXT: retl
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bb:
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%tmp = alloca i64, align 8
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%tmp1 = load i16, i16* @var_22, align 2
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%tmp2 = zext i16 %tmp1 to i32
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%tmp3 = load i16, i16* @var_27, align 2
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%tmp4 = zext i16 %tmp3 to i32
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%tmp5 = xor i32 %tmp2, %tmp4
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%tmp6 = load i16, i16* @var_27, align 2
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%tmp7 = zext i16 %tmp6 to i32
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%tmp8 = xor i32 %tmp5, %tmp7
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%tmp9 = sext i32 %tmp8 to i64
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store i64 %tmp9, i64* %tmp, align 8
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%tmp10 = load i16, i16* @var_22, align 2
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%tmp11 = zext i16 %tmp10 to i32
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%tmp12 = load i16, i16* @var_27, align 2
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%tmp13 = zext i16 %tmp12 to i32
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%tmp14 = xor i32 %tmp11, %tmp13
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%tmp15 = load i16, i16* @var_27, align 2
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%tmp16 = zext i16 %tmp15 to i32
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%tmp17 = xor i32 %tmp14, %tmp16
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%tmp18 = sext i32 %tmp17 to i64
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%tmp19 = load i16, i16* @var_27, align 2
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%tmp20 = zext i16 %tmp19 to i32
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%tmp21 = sub nsw i32 %tmp20, 16610
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%tmp22 = zext i32 %tmp21 to i64
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%tmp23 = ashr i64 %tmp18, %tmp22
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%tmp24 = trunc i64 %tmp23 to i8
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store i8 %tmp24, i8* undef, align 1
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ret void
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}
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