8ea72a8201
These instructions implicitly operate on ST0, but we don't currently add that information to the MachineInstr. We also don't add it the tablegen definitions either. For the most part this doesn't cause any problems because the stackifying occurs after register allocation. All the instructions are marked as having side effects so the postRA scheduler won't reorder them amongst themselves. But nothing stops inline assembly using X87 instructions from being reordered around other x87 instructions if that inline assembly wasn't marked volatile. The two test cases I've identified so far in PR40539 involve loads and stores used to set up the inline assembly or capture the results of the inline assembly ending up in the wrong order. This patch adds implicit ST0 uses/defs to the load/store instructions to prevent this from happening. I plan to fix all of the FP instructions, but the binops are bit trickier to get right. So I've chosen fixing the known test cases as a good first step. I think we also need to update the tablegen descriptions so MS inline assembly infers the right clobbers, but I haven't checked that yet. Differential Revision: https://reviews.llvm.org/D57644 llvm-svn: 353070
71 lines
2.3 KiB
LLVM
71 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=pentium4 | FileCheck %s
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@f1 = global float 1.000000e+00, align 4
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define zeroext i1 @_Z9test_log2v() {
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; CHECK-LABEL: _Z9test_log2v:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: flds f1
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; CHECK-NEXT: #APP
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; CHECK-NEXT: fld1
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; CHECK-NEXT: fxch %st(1)
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; CHECK-NEXT: fyl2x
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: fstps (%esp)
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: cmpeqss (%esp), %xmm0
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; CHECK-NEXT: movd %xmm0, %eax
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; CHECK-NEXT: andl $1, %eax
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: popl %ecx
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; CHECK-NEXT: .cfi_def_cfa_offset 4
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; CHECK-NEXT: retl
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entry:
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%0 = load float, float* @f1, align 4
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%1 = fpext float %0 to x86_fp80
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%2 = tail call x86_fp80 asm "fld1; fxch; fyl2x", "={st},0,~{st(1)},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %1)
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%conv = fptrunc x86_fp80 %2 to float
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%3 = fcmp oeq float %conv, 0.000000e+00
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ret i1 %3
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}
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@fpi = external global float, align 4
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define zeroext i1 @_Z8test_cosv() {
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; CHECK-LABEL: _Z8test_cosv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: subl $8, %esp
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; CHECK-NEXT: .cfi_def_cfa_offset 12
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; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; CHECK-NEXT: divss {{\.LCPI.*}}, %xmm0
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; CHECK-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
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; CHECK-NEXT: flds {{[0-9]+}}(%esp)
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; CHECK-NEXT: #APP
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; CHECK-NEXT: fcos
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: fstps (%esp)
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; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; CHECK-NEXT: ucomiss %xmm0, %xmm1
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; CHECK-NEXT: setae %cl
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; CHECK-NEXT: ucomiss {{\.LCPI.*}}, %xmm0
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; CHECK-NEXT: setae %al
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; CHECK-NEXT: andb %cl, %al
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; CHECK-NEXT: addl $8, %esp
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; CHECK-NEXT: .cfi_def_cfa_offset 4
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; CHECK-NEXT: retl
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entry:
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%0 = load float, float* @fpi, align 4
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%div = fdiv float %0, 6.000000e+00
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%1 = fpext float %div to x86_fp80
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%2 = tail call x86_fp80 asm "fcos", "={st},0,~{dirflag},~{fpsr},~{flags}"(x86_fp80 %1)
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%conv = fptrunc x86_fp80 %2 to float
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%cmp = fcmp ole float %conv, 0x3FEBD70A40000000
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%cmp1 = fcmp oge float %conv, 0x3FEB851EC0000000
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%or.cond = and i1 %cmp, %cmp1
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ret i1 %or.cond
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}
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