76eca062ea
1. LiveIntervals now implement a 4 slot per instruction model. Load, Use, Def and a Store slot. This is required in order to correctly represent caller saved register clobbering on function calls, register reuse in the same instruction (def resues last use) and also spill code added later by the allocator. The previous representation (2 slots per instruction) was insufficient and as a result was causing subtle bugs. 2. Fixes in spill code generation. This was the major cause of failures in the test suite. 3. Linear scan now has core support for folding memory operands. This is untested and not enabled (the live interval update function does not attempt to fold loads/stores in instructions). 4. Lots of improvements in the debugging output of both live intervals and linear scan. Give it a try... it is beautiful :-) In summary the above fixes all the issues with the recent reserved register elimination changes and get the allocator very close to the next big step: folding memory operands. llvm-svn: 11654
681 lines
24 KiB
C++
681 lines
24 KiB
C++
//===-- LiveIntervals.cpp - Live Interval Analysis ------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveInterval analysis pass which is used
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// by the Linear Scan Register allocator. This pass linearizes the
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// basic blocks of the function in DFS order and uses the
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// LiveVariables pass to conservatively compute live intervals for
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// each virtual and physical register.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "liveintervals"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/CFG.h"
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#include "Support/CommandLine.h"
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#include "Support/Debug.h"
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#include "Support/Statistic.h"
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#include "Support/STLExtras.h"
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#include <cmath>
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#include <iostream>
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#include <limits>
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using namespace llvm;
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namespace {
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RegisterAnalysis<LiveIntervals> X("liveintervals",
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"Live Interval Analysis");
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Statistic<> numIntervals("liveintervals", "Number of intervals");
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Statistic<> numJoined ("liveintervals", "Number of joined intervals");
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Statistic<> numPeep ("liveintervals", "Number of identity moves "
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"eliminated after coalescing");
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Statistic<> numFolded ("liveintervals", "Number of register operands "
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"folded");
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cl::opt<bool>
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join("join-liveintervals",
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cl::desc("Join compatible live intervals"),
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cl::init(true));
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};
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void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
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{
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AU.addPreserved<LiveVariables>();
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AU.addRequired<LiveVariables>();
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AU.addPreservedID(PHIEliminationID);
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AU.addRequiredID(PHIEliminationID);
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AU.addRequiredID(TwoAddressInstructionPassID);
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AU.addRequired<LoopInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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void LiveIntervals::releaseMemory()
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{
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mbbi2mbbMap_.clear();
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mi2iMap_.clear();
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i2miMap_.clear();
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r2iMap_.clear();
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r2rMap_.clear();
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intervals_.clear();
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}
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/// runOnMachineFunction - Register allocate the whole function
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///
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bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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mf_ = &fn;
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tm_ = &fn.getTarget();
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mri_ = tm_->getRegisterInfo();
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lv_ = &getAnalysis<LiveVariables>();
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// number MachineInstrs
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unsigned miIndex = 0;
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for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end();
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mbb != mbbEnd; ++mbb) {
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const std::pair<MachineBasicBlock*, unsigned>& entry =
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lv_->getMachineBasicBlockInfo(mbb);
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bool inserted = mbbi2mbbMap_.insert(std::make_pair(entry.second,
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entry.first)).second;
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assert(inserted && "multiple index -> MachineBasicBlock");
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for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
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mi != miEnd; ++mi) {
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inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second;
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assert(inserted && "multiple MachineInstr -> index mappings");
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i2miMap_.push_back(mi);
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miIndex += InstrSlots::NUM;
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}
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}
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computeIntervals();
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numIntervals += intervals_.size();
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// join intervals if requested
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if (join) joinIntervals();
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// perform a final pass over the instructions and compute spill
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// weights, coalesce virtual registers and remove identity moves
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const LoopInfo& loopInfo = getAnalysis<LoopInfo>();
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const TargetInstrInfo& tii = tm_->getInstrInfo();
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for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
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mbbi != mbbe; ++mbbi) {
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MachineBasicBlock* mbb = mbbi;
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unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
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for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
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mii != mie; ) {
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for (unsigned i = 0; i < mii->getNumOperands(); ++i) {
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const MachineOperand& mop = mii->getOperand(i);
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if (mop.isRegister()) {
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// replace register with representative register
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unsigned reg = rep(mop.getReg());
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mii->SetMachineOperandReg(i, reg);
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if (MRegisterInfo::isVirtualRegister(reg)) {
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Reg2IntervalMap::iterator r2iit = r2iMap_.find(reg);
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assert(r2iit != r2iMap_.end());
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r2iit->second->weight += pow(10.0F, loopDepth);
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}
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}
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}
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// if the move is now an identity move delete it
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unsigned srcReg, dstReg;
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if (tii.isMoveInstr(*mii, srcReg, dstReg) && srcReg == dstReg) {
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// remove index -> MachineInstr and
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// MachineInstr -> index mappings
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Mi2IndexMap::iterator mi2i = mi2iMap_.find(mii);
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if (mi2i != mi2iMap_.end()) {
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i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
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mi2iMap_.erase(mi2i);
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}
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mii = mbbi->erase(mii);
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++numPeep;
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}
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else
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++mii;
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}
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}
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intervals_.sort(StartPointComp());
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DEBUG(std::cerr << "********** INTERVALS **********\n");
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DEBUG(std::copy(intervals_.begin(), intervals_.end(),
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std::ostream_iterator<Interval>(std::cerr, "\n")));
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DEBUG(std::cerr << "********** MACHINEINSTRS **********\n");
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DEBUG(
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for (unsigned i = 0; i != i2miMap_.size(); ++i) {
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if (const MachineInstr* mi = i2miMap_[i]) {
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std:: cerr << i * InstrSlots::NUM << '\t';
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mi->print(std::cerr, *tm_);
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}
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});
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return true;
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}
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void LiveIntervals::updateSpilledInterval(Interval& li, int slot)
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{
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assert(li.weight != std::numeric_limits<float>::infinity() &&
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"attempt to spill already spilled interval!");
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Interval::Ranges oldRanges;
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swap(oldRanges, li.ranges);
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DEBUG(std::cerr << "\t\t\t\tupdating interval: " << li);
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for (Interval::Ranges::iterator i = oldRanges.begin(), e = oldRanges.end();
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i != e; ++i) {
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unsigned index = getBaseIndex(i->first);
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unsigned end = getBaseIndex(i->second-1) + InstrSlots::NUM;
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for (; index < end; index += InstrSlots::NUM) {
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// skip deleted instructions
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while (!getInstructionFromIndex(index)) index += InstrSlots::NUM;
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MachineBasicBlock::iterator mi = getInstructionFromIndex(index);
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for (unsigned i = 0; i < mi->getNumOperands(); ++i) {
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MachineOperand& mop = mi->getOperand(i);
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if (mop.isRegister() && mop.getReg() == li.reg) {
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// This is tricky. We need to add information in
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// the interval about the spill code so we have to
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// use our extra load/store slots.
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//
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// If we have a use we are going to have a load so
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// we start the interval from the load slot
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// onwards. Otherwise we start from the def slot.
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unsigned start = (mop.isUse() ?
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getLoadIndex(index) :
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getDefIndex(index));
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// If we have a def we are going to have a store
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// right after it so we end the interval after the
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// use of the next instruction. Otherwise we end
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// after the use of this instruction.
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unsigned end = 1 + (mop.isDef() ?
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getUseIndex(index+InstrSlots::NUM) :
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getUseIndex(index));
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li.addRange(start, end);
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}
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}
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}
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}
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// the new spill weight is now infinity as it cannot be spilled again
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li.weight = std::numeric_limits<float>::infinity();
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DEBUG(std::cerr << '\n');
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}
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void LiveIntervals::printRegName(unsigned reg) const
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{
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if (MRegisterInfo::isPhysicalRegister(reg))
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std::cerr << mri_->getName(reg);
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else
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std::cerr << "%reg" << reg;
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}
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void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock* mbb,
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MachineBasicBlock::iterator mi,
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unsigned reg)
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{
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DEBUG(std::cerr << "\t\tregister: "; printRegName(reg));
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LiveVariables::VarInfo& vi = lv_->getVarInfo(reg);
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Interval* interval = 0;
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Reg2IntervalMap::iterator r2iit = r2iMap_.lower_bound(reg);
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if (r2iit == r2iMap_.end() || r2iit->first != reg) {
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// add new interval
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intervals_.push_back(Interval(reg));
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// update interval index for this register
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r2iMap_.insert(r2iit, std::make_pair(reg, --intervals_.end()));
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interval = &intervals_.back();
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// iterate over all of the blocks that the variable is
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// completely live in, adding them to the live
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// interval. obviously we only need to do this once.
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for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
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if (vi.AliveBlocks[i]) {
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MachineBasicBlock* mbb = lv_->getIndexMachineBasicBlock(i);
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if (!mbb->empty()) {
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interval->addRange(
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getInstructionIndex(&mbb->front()),
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getInstructionIndex(&mbb->back()) + InstrSlots::NUM);
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}
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}
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}
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}
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else {
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interval = &*r2iit->second;
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}
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unsigned baseIndex = getInstructionIndex(mi);
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bool killedInDefiningBasicBlock = false;
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for (int i = 0, e = vi.Kills.size(); i != e; ++i) {
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MachineBasicBlock* killerBlock = vi.Kills[i].first;
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MachineInstr* killerInstr = vi.Kills[i].second;
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unsigned start = (mbb == killerBlock ?
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getDefIndex(baseIndex) :
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getInstructionIndex(&killerBlock->front()));
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unsigned end = (killerInstr == mi ?
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// dead
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start + 1 :
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// killed
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getUseIndex(getInstructionIndex(killerInstr))+1);
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// we do not want to add invalid ranges. these can happen when
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// a variable has its latest use and is redefined later on in
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// the same basic block (common with variables introduced by
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// PHI elimination)
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if (start < end) {
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killedInDefiningBasicBlock |= mbb == killerBlock;
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interval->addRange(start, end);
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}
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}
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if (!killedInDefiningBasicBlock) {
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unsigned end = getInstructionIndex(&mbb->back()) + InstrSlots::NUM;
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interval->addRange(getDefIndex(baseIndex), end);
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}
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DEBUG(std::cerr << '\n');
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}
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void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock* mbb,
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MachineBasicBlock::iterator mi,
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unsigned reg)
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{
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DEBUG(std::cerr << "\t\tregister: "; printRegName(reg));
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typedef LiveVariables::killed_iterator KillIter;
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MachineBasicBlock::iterator e = mbb->end();
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unsigned baseIndex = getInstructionIndex(mi);
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unsigned start = getDefIndex(baseIndex);
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unsigned end = start;
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// a variable can be dead by the instruction defining it
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for (KillIter ki = lv_->dead_begin(mi), ke = lv_->dead_end(mi);
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ki != ke; ++ki) {
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if (reg == ki->second) {
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DEBUG(std::cerr << " dead");
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end = getDefIndex(start) + 1;
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goto exit;
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}
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}
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// a variable can only be killed by subsequent instructions
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do {
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++mi;
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baseIndex += InstrSlots::NUM;
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for (KillIter ki = lv_->killed_begin(mi), ke = lv_->killed_end(mi);
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ki != ke; ++ki) {
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if (reg == ki->second) {
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DEBUG(std::cerr << " killed");
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end = getUseIndex(baseIndex) + 1;
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goto exit;
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}
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}
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} while (mi != e);
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exit:
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assert(start < end && "did not find end of interval?");
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Reg2IntervalMap::iterator r2iit = r2iMap_.lower_bound(reg);
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if (r2iit != r2iMap_.end() && r2iit->first == reg) {
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r2iit->second->addRange(start, end);
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}
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else {
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intervals_.push_back(Interval(reg));
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// update interval index for this register
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r2iMap_.insert(r2iit, std::make_pair(reg, --intervals_.end()));
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intervals_.back().addRange(start, end);
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}
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DEBUG(std::cerr << '\n');
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}
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void LiveIntervals::handleRegisterDef(MachineBasicBlock* mbb,
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MachineBasicBlock::iterator mi,
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unsigned reg)
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{
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if (MRegisterInfo::isPhysicalRegister(reg)) {
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if (lv_->getAllocatablePhysicalRegisters()[reg]) {
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handlePhysicalRegisterDef(mbb, mi, reg);
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for (const unsigned* as = mri_->getAliasSet(reg); *as; ++as)
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handlePhysicalRegisterDef(mbb, mi, *as);
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}
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}
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else {
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handleVirtualRegisterDef(mbb, mi, reg);
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}
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}
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unsigned LiveIntervals::getInstructionIndex(MachineInstr* instr) const
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{
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Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
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return (it == mi2iMap_.end() ?
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std::numeric_limits<unsigned>::max() :
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it->second);
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}
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MachineInstr* LiveIntervals::getInstructionFromIndex(unsigned index) const
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{
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index /= InstrSlots::NUM; // convert index to vector index
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assert(index < i2miMap_.size() &&
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"index does not correspond to an instruction");
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return i2miMap_[index];
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}
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/// computeIntervals - computes the live intervals for virtual
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/// registers. for some ordering of the machine instructions [1,N] a
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/// live interval is an interval [i, j) where 1 <= i <= j < N for
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/// which a variable is live
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void LiveIntervals::computeIntervals()
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{
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DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n");
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DEBUG(std::cerr << "********** Function: "
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<< mf_->getFunction()->getName() << '\n');
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for (MbbIndex2MbbMap::iterator
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it = mbbi2mbbMap_.begin(), itEnd = mbbi2mbbMap_.end();
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it != itEnd; ++it) {
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MachineBasicBlock* mbb = it->second;
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DEBUG(std::cerr << mbb->getBasicBlock()->getName() << ":\n");
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for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
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mi != miEnd; ++mi) {
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const TargetInstrDescriptor& tid =
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tm_->getInstrInfo().get(mi->getOpcode());
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DEBUG(std::cerr << getInstructionIndex(mi) << "\t";
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mi->print(std::cerr, *tm_));
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// handle implicit defs
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for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
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handleRegisterDef(mbb, mi, *id);
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// handle explicit defs
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for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
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MachineOperand& mop = mi->getOperand(i);
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// handle register defs - build intervals
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if (mop.isRegister() && mop.isDef())
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handleRegisterDef(mbb, mi, mop.getReg());
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}
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}
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}
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}
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unsigned LiveIntervals::rep(unsigned reg)
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{
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Reg2RegMap::iterator it = r2rMap_.find(reg);
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if (it != r2rMap_.end())
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return it->second = rep(it->second);
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return reg;
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}
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void LiveIntervals::joinIntervals()
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{
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DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n");
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const TargetInstrInfo& tii = tm_->getInstrInfo();
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for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
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mbbi != mbbe; ++mbbi) {
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MachineBasicBlock* mbb = mbbi;
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DEBUG(std::cerr << mbb->getBasicBlock()->getName() << ":\n");
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for (MachineBasicBlock::iterator mi = mbb->begin(), mie = mbb->end();
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mi != mie; ++mi) {
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const TargetInstrDescriptor& tid =
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tm_->getInstrInfo().get(mi->getOpcode());
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DEBUG(std::cerr << getInstructionIndex(mi) << '\t';
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mi->print(std::cerr, *tm_););
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// we only join virtual registers with allocatable
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// physical registers since we do not have liveness information
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// on not allocatable physical registers
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unsigned regA, regB;
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if (tii.isMoveInstr(*mi, regA, regB) &&
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(MRegisterInfo::isVirtualRegister(regA) ||
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lv_->getAllocatablePhysicalRegisters()[regA]) &&
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(MRegisterInfo::isVirtualRegister(regB) ||
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lv_->getAllocatablePhysicalRegisters()[regB])) {
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// get representative registers
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regA = rep(regA);
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regB = rep(regB);
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// if they are already joined we continue
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if (regA == regB)
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continue;
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Reg2IntervalMap::iterator r2iA = r2iMap_.find(regA);
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assert(r2iA != r2iMap_.end());
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Reg2IntervalMap::iterator r2iB = r2iMap_.find(regB);
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assert(r2iB != r2iMap_.end());
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Intervals::iterator intA = r2iA->second;
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Intervals::iterator intB = r2iB->second;
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// both A and B are virtual registers
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if (MRegisterInfo::isVirtualRegister(intA->reg) &&
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MRegisterInfo::isVirtualRegister(intB->reg)) {
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const TargetRegisterClass *rcA, *rcB;
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rcA = mf_->getSSARegMap()->getRegClass(intA->reg);
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rcB = mf_->getSSARegMap()->getRegClass(intB->reg);
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assert(rcA == rcB && "registers must be of the same class");
|
|
|
|
// if their intervals do not overlap we join them
|
|
if (!intB->overlaps(*intA)) {
|
|
intA->join(*intB);
|
|
r2iB->second = r2iA->second;
|
|
r2rMap_.insert(std::make_pair(intB->reg, intA->reg));
|
|
intervals_.erase(intB);
|
|
++numJoined;
|
|
}
|
|
}
|
|
else if (MRegisterInfo::isPhysicalRegister(intA->reg) ^
|
|
MRegisterInfo::isPhysicalRegister(intB->reg)) {
|
|
if (MRegisterInfo::isPhysicalRegister(intB->reg)) {
|
|
std::swap(regA, regB);
|
|
std::swap(intA, intB);
|
|
std::swap(r2iA, r2iB);
|
|
}
|
|
|
|
assert(MRegisterInfo::isPhysicalRegister(intA->reg) &&
|
|
MRegisterInfo::isVirtualRegister(intB->reg) &&
|
|
"A must be physical and B must be virtual");
|
|
|
|
if (!intA->overlaps(*intB) &&
|
|
!overlapsAliases(*intA, *intB)) {
|
|
intA->join(*intB);
|
|
r2iB->second = r2iA->second;
|
|
r2rMap_.insert(std::make_pair(intB->reg, intA->reg));
|
|
intervals_.erase(intB);
|
|
++numJoined;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
bool LiveIntervals::overlapsAliases(const Interval& lhs,
|
|
const Interval& rhs) const
|
|
{
|
|
assert(MRegisterInfo::isPhysicalRegister(lhs.reg) &&
|
|
"first interval must describe a physical register");
|
|
|
|
for (const unsigned* as = mri_->getAliasSet(lhs.reg); *as; ++as) {
|
|
Reg2IntervalMap::const_iterator r2i = r2iMap_.find(*as);
|
|
assert(r2i != r2iMap_.end() && "alias does not have interval?");
|
|
if (rhs.overlaps(*r2i->second))
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
LiveIntervals::Interval::Interval(unsigned r)
|
|
: reg(r),
|
|
weight((MRegisterInfo::isPhysicalRegister(r) ?
|
|
std::numeric_limits<float>::infinity() : 0.0F))
|
|
{
|
|
|
|
}
|
|
|
|
bool LiveIntervals::Interval::spilled() const
|
|
{
|
|
return (weight == std::numeric_limits<float>::infinity() &&
|
|
MRegisterInfo::isVirtualRegister(reg));
|
|
}
|
|
|
|
// An example for liveAt():
|
|
//
|
|
// this = [1,4), liveAt(0) will return false. The instruction defining
|
|
// this spans slots [0,3]. The interval belongs to an spilled
|
|
// definition of the variable it represents. This is because slot 1 is
|
|
// used (def slot) and spans up to slot 3 (store slot).
|
|
//
|
|
bool LiveIntervals::Interval::liveAt(unsigned index) const
|
|
{
|
|
Range dummy(index, index+1);
|
|
Ranges::const_iterator r = std::upper_bound(ranges.begin(),
|
|
ranges.end(),
|
|
dummy);
|
|
if (r == ranges.begin())
|
|
return false;
|
|
|
|
--r;
|
|
return index >= r->first && index < r->second;
|
|
}
|
|
|
|
// An example for overlaps():
|
|
//
|
|
// 0: A = ...
|
|
// 4: B = ...
|
|
// 8: C = A + B ;; last use of A
|
|
//
|
|
// The live intervals should look like:
|
|
//
|
|
// A = [3, 11)
|
|
// B = [7, x)
|
|
// C = [11, y)
|
|
//
|
|
// A->overlaps(C) should return false since we want to be able to join
|
|
// A and C.
|
|
bool LiveIntervals::Interval::overlaps(const Interval& other) const
|
|
{
|
|
Ranges::const_iterator i = ranges.begin();
|
|
Ranges::const_iterator ie = ranges.end();
|
|
Ranges::const_iterator j = other.ranges.begin();
|
|
Ranges::const_iterator je = other.ranges.end();
|
|
if (i->first < j->first) {
|
|
i = std::upper_bound(i, ie, *j);
|
|
if (i != ranges.begin()) --i;
|
|
}
|
|
else if (j->first < i->first) {
|
|
j = std::upper_bound(j, je, *i);
|
|
if (j != other.ranges.begin()) --j;
|
|
}
|
|
|
|
while (i != ie && j != je) {
|
|
if (i->first == j->first) {
|
|
return true;
|
|
}
|
|
else {
|
|
if (i->first > j->first) {
|
|
swap(i, j);
|
|
swap(ie, je);
|
|
}
|
|
assert(i->first < j->first);
|
|
|
|
if (i->second > j->first) {
|
|
return true;
|
|
}
|
|
else {
|
|
++i;
|
|
}
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
void LiveIntervals::Interval::addRange(unsigned start, unsigned end)
|
|
{
|
|
assert(start < end && "Invalid range to add!");
|
|
DEBUG(std::cerr << " +[" << start << ',' << end << ")");
|
|
//assert(start < end && "invalid range?");
|
|
Range range = std::make_pair(start, end);
|
|
Ranges::iterator it =
|
|
ranges.insert(std::upper_bound(ranges.begin(), ranges.end(), range),
|
|
range);
|
|
|
|
it = mergeRangesForward(it);
|
|
it = mergeRangesBackward(it);
|
|
}
|
|
|
|
void LiveIntervals::Interval::join(const LiveIntervals::Interval& other)
|
|
{
|
|
DEBUG(std::cerr << "\t\tjoining " << *this << " with " << other << '\n');
|
|
Ranges::iterator cur = ranges.begin();
|
|
|
|
for (Ranges::const_iterator i = other.ranges.begin(),
|
|
e = other.ranges.end(); i != e; ++i) {
|
|
cur = ranges.insert(std::upper_bound(cur, ranges.end(), *i), *i);
|
|
cur = mergeRangesForward(cur);
|
|
cur = mergeRangesBackward(cur);
|
|
}
|
|
if (MRegisterInfo::isVirtualRegister(reg))
|
|
weight += other.weight;
|
|
}
|
|
|
|
LiveIntervals::Interval::Ranges::iterator
|
|
LiveIntervals::Interval::mergeRangesForward(Ranges::iterator it)
|
|
{
|
|
for (Ranges::iterator n = next(it);
|
|
n != ranges.end() && ((it->second & 1) + it->second) >= n->first; ) {
|
|
it->second = std::max(it->second, n->second);
|
|
n = ranges.erase(n);
|
|
}
|
|
return it;
|
|
}
|
|
|
|
LiveIntervals::Interval::Ranges::iterator
|
|
LiveIntervals::Interval::mergeRangesBackward(Ranges::iterator it)
|
|
{
|
|
while (it != ranges.begin()) {
|
|
Ranges::iterator p = prior(it);
|
|
if (it->first > ((p->second & 1) + p->second)) break;
|
|
|
|
it->first = std::min(it->first, p->first);
|
|
it->second = std::max(it->second, p->second);
|
|
it = ranges.erase(p);
|
|
}
|
|
|
|
return it;
|
|
}
|
|
|
|
std::ostream& llvm::operator<<(std::ostream& os,
|
|
const LiveIntervals::Interval& li)
|
|
{
|
|
os << "%reg" << li.reg << ',' << li.weight << " = ";
|
|
if (li.empty())
|
|
return os << "EMPTY";
|
|
for (LiveIntervals::Interval::Ranges::const_iterator
|
|
i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
|
|
os << "[" << i->first << "," << i->second << ")";
|
|
}
|
|
return os;
|
|
}
|