8f4b7e94a2
Added cost estimation for switch instruction, updated costs of branches, fixed phi cost. Had to increase `-amdgpu-unroll-threshold-if` default value since conditional branch cost (size) was corrected to higher value. Test renamed to "control-flow.ll". Removed redundant code in `X86TTIImpl::getCFInstrCost()` and `PPCTTIImpl::getCFInstrCost()`. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D96805
53 lines
1.6 KiB
LLVM
53 lines
1.6 KiB
LLVM
; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck --check-prefixes=ALL,SPEED %s
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; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck --check-prefixes=ALL,SIZE %s
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; ALL-LABEL: 'test_br_cost'
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; SPEED: estimated cost of 7 for instruction: br i1
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; SPEED: estimated cost of 4 for instruction: br label
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; SPEED: estimated cost of 1 for instruction: %phi = phi i32 [
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; SPEED: estimated cost of 10 for instruction: ret void
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; SIZE: estimated cost of 5 for instruction: br i1
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; SIZE: estimated cost of 1 for instruction: br label
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; SIZE: estimated cost of 1 for instruction: %phi = phi i32 [
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; SIZE: estimated cost of 1 for instruction: ret void
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define amdgpu_kernel void @test_br_cost(i32 addrspace(1)* %out, i32 addrspace(1)* %vaddr, i32 %b) #0 {
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bb0:
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br i1 undef, label %bb1, label %bb2
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bb1:
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%vec = load i32, i32 addrspace(1)* %vaddr
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%add = add i32 %vec, %b
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store i32 %add, i32 addrspace(1)* %out
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br label %bb2
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bb2:
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%phi = phi i32 [ %b, %bb0 ], [ %add, %bb1 ]
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ret void
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}
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; ALL-LABEL: 'test_switch_cost'
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; SPEED: estimated cost of 24 for instruction: switch
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; SIZE: estimated cost of 18 for instruction: switch
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define amdgpu_kernel void @test_switch_cost(i32 %a) #0 {
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entry:
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switch i32 %a, label %default [
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i32 0, label %case0
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i32 1, label %case1
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]
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case0:
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store volatile i32 undef, i32 addrspace(1)* undef
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ret void
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case1:
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store volatile i32 undef, i32 addrspace(1)* undef
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ret void
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default:
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store volatile i32 undef, i32 addrspace(1)* undef
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ret void
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end:
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ret void
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}
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