3bffb1cd0e
Replace individual operands GLC, SLC, and DLC with a single cache_policy bitmask operand. This will reduce the number of operands in MIR and I hope the amount of code. These operands are mostly 0 anyway. Additional advantage that parser will accept these flags in any order unlike now. Differential Revision: https://reviews.llvm.org/D96469
21 lines
718 B
YAML
21 lines
718 B
YAML
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass machine-scheduler %s -o - | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: cluster_flat_loads
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# GCN: FLAT_LOAD_DWORD %0, 0
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# GCN-NEXT: FLAT_LOAD_DWORD %0, 4
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# GCN-NEXT: V_ADD_F32_e64
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name: cluster_flat_loads
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vreg_64 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: vgpr_32 }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
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%2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $mode, implicit $exec
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%3 = FLAT_LOAD_DWORD %0, 4, 0, implicit $exec, implicit $flat_scr :: (load 4)
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...
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