229e118559
For targets that support xnack replay feature (gfx8+), the multi-dword scalar loads shouldn't clobber any register that holds the src address. The constrained version of the scalar loads have the early clobber flag attached to the dst operand to restrict RA from re-allocating any of the src regs for its dst operand.
4250 lines
168 KiB
LLVM
4250 lines
168 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX6 %s
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; RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12 %s
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define amdgpu_kernel void @v_clamp_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
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; GFX6-LABEL: v_clamp_f32:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
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; GFX6-NEXT: s_mov_b32 s7, 0xf000
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; GFX6-NEXT: s_mov_b32 s6, 0
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; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX6-NEXT: v_mov_b32_e32 v1, 0
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
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; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
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; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
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; GFX6-NEXT: s_waitcnt vmcnt(0)
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; GFX6-NEXT: v_max_f32_e64 v2, v2, v2 clamp
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; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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; GFX6-NEXT: s_endpgm
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;
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; GFX8-LABEL: v_clamp_f32:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
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; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: v_mov_b32_e32 v1, s3
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
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; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; GFX8-NEXT: flat_load_dword v3, v[0:1]
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; GFX8-NEXT: v_mov_b32_e32 v1, s1
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
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; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; GFX8-NEXT: s_waitcnt vmcnt(0)
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; GFX8-NEXT: v_max_f32_e64 v2, v3, v3 clamp
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; GFX8-NEXT: flat_store_dword v[0:1], v2
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; GFX8-NEXT: s_endpgm
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;
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; GFX9-LABEL: v_clamp_f32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
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; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_max_f32_e64 v1, v1, v1 clamp
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; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
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; GFX9-NEXT: s_endpgm
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;
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; GFX11-LABEL: v_clamp_f32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
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; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: v_max_f32_e64 v1, v1, v1 clamp
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; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: v_clamp_f32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
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; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp
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; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
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; GFX12-NEXT: s_nop 0
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; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
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%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
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%a = load float, ptr addrspace(1) %gep0
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%max = call float @llvm.maxnum.f32(float %a, float 0.0)
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%med = call float @llvm.minnum.f32(float %max, float 1.0)
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store float %med, ptr addrspace(1) %out.gep
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ret void
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}
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define amdgpu_kernel void @v_clamp_neg_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
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; GFX6-LABEL: v_clamp_neg_f32:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
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; GFX6-NEXT: s_mov_b32 s7, 0xf000
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; GFX6-NEXT: s_mov_b32 s6, 0
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; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX6-NEXT: v_mov_b32_e32 v1, 0
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
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; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
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; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
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; GFX6-NEXT: s_waitcnt vmcnt(0)
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; GFX6-NEXT: v_max_f32_e64 v2, -v2, -v2 clamp
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; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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; GFX6-NEXT: s_endpgm
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;
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; GFX8-LABEL: v_clamp_neg_f32:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
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; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: v_mov_b32_e32 v1, s3
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
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; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; GFX8-NEXT: flat_load_dword v3, v[0:1]
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; GFX8-NEXT: v_mov_b32_e32 v1, s1
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
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; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; GFX8-NEXT: s_waitcnt vmcnt(0)
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; GFX8-NEXT: v_max_f32_e64 v2, -v3, -v3 clamp
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; GFX8-NEXT: flat_store_dword v[0:1], v2
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; GFX8-NEXT: s_endpgm
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;
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; GFX9-LABEL: v_clamp_neg_f32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
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; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_max_f32_e64 v1, -v1, -v1 clamp
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; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
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; GFX9-NEXT: s_endpgm
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;
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; GFX11-LABEL: v_clamp_neg_f32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
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; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: v_max_f32_e64 v1, -v1, -v1 clamp
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; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: v_clamp_neg_f32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
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; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: v_max_num_f32_e64 v1, -v1, -v1 clamp
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; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
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; GFX12-NEXT: s_nop 0
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; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
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%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
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%a = load float, ptr addrspace(1) %gep0
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%fneg.a = fneg float %a
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%max = call float @llvm.maxnum.f32(float %fneg.a, float 0.0)
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%med = call float @llvm.minnum.f32(float %max, float 1.0)
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store float %med, ptr addrspace(1) %out.gep
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ret void
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}
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define amdgpu_kernel void @v_clamp_negabs_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
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; GFX6-LABEL: v_clamp_negabs_f32:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
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; GFX6-NEXT: s_mov_b32 s7, 0xf000
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; GFX6-NEXT: s_mov_b32 s6, 0
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; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX6-NEXT: v_mov_b32_e32 v1, 0
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
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; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
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; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
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; GFX6-NEXT: s_waitcnt vmcnt(0)
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; GFX6-NEXT: v_max_f32_e64 v2, -|v2|, -|v2| clamp
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; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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; GFX6-NEXT: s_endpgm
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;
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; GFX8-LABEL: v_clamp_negabs_f32:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
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; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: v_mov_b32_e32 v1, s3
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
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; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; GFX8-NEXT: flat_load_dword v3, v[0:1]
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; GFX8-NEXT: v_mov_b32_e32 v1, s1
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
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; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; GFX8-NEXT: s_waitcnt vmcnt(0)
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; GFX8-NEXT: v_max_f32_e64 v2, -|v3|, -|v3| clamp
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; GFX8-NEXT: flat_store_dword v[0:1], v2
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; GFX8-NEXT: s_endpgm
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;
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; GFX9-LABEL: v_clamp_negabs_f32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
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; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_max_f32_e64 v1, -|v1|, -|v1| clamp
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; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
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; GFX9-NEXT: s_endpgm
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;
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; GFX11-LABEL: v_clamp_negabs_f32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
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; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: v_max_f32_e64 v1, -|v1|, -|v1| clamp
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; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: v_clamp_negabs_f32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
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; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: v_max_num_f32_e64 v1, -|v1|, -|v1| clamp
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; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
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; GFX12-NEXT: s_nop 0
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; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
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%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
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%a = load float, ptr addrspace(1) %gep0
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%fabs.a = call float @llvm.fabs.f32(float %a)
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%fneg.fabs.a = fneg float %fabs.a
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%max = call float @llvm.maxnum.f32(float %fneg.fabs.a, float 0.0)
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%med = call float @llvm.minnum.f32(float %max, float 1.0)
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store float %med, ptr addrspace(1) %out.gep
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ret void
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}
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define amdgpu_kernel void @v_clamp_negzero_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
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; GFX6-LABEL: v_clamp_negzero_f32:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
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; GFX6-NEXT: s_mov_b32 s7, 0xf000
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; GFX6-NEXT: s_mov_b32 s6, 0
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; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX6-NEXT: v_mov_b32_e32 v1, 0
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
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; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
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; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
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; GFX6-NEXT: s_waitcnt vmcnt(0)
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; GFX6-NEXT: v_add_f32_e32 v2, 0.5, v2
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; GFX6-NEXT: v_max_f32_e32 v2, 0x80000000, v2
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; GFX6-NEXT: v_min_f32_e32 v2, 1.0, v2
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; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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; GFX6-NEXT: s_endpgm
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;
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; GFX8-LABEL: v_clamp_negzero_f32:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_add_f32_e32 v2, 0.5, v3
|
|
; GFX8-NEXT: v_max_f32_e32 v2, 0x80000000, v2
|
|
; GFX8-NEXT: v_min_f32_e32 v2, 1.0, v2
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_negzero_f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_f32_e32 v1, 0.5, v1
|
|
; GFX9-NEXT: v_max_f32_e32 v1, 0x80000000, v1
|
|
; GFX9-NEXT: v_min_f32_e32 v1, 1.0, v1
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_negzero_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_add_f32_e32 v1, 0.5, v1
|
|
; GFX11-NEXT: v_maxmin_f32 v1, v1, 0x80000000, 1.0
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_negzero_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_add_f32_e32 v1, 0.5, v1
|
|
; GFX12-NEXT: v_maxmin_num_f32 v1, v1, 0x80000000, 1.0
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%add = fadd nnan float %a, 0.5
|
|
%max = call float @llvm.maxnum.f32(float %add, float -0.0)
|
|
%med = call float @llvm.minnum.f32(float %max, float 1.0)
|
|
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
; FIXME: Weird inconsistency in how -0.0 is treated. Accepted if clamp
|
|
; matched through med3, not if directly. Is this correct?
|
|
define amdgpu_kernel void @v_clamp_negzero_maybe_snan_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_negzero_maybe_snan_f32:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_mul_f32_e32 v2, 1.0, v2
|
|
; GFX6-NEXT: v_max_f32_e32 v2, 0x80000000, v2
|
|
; GFX6-NEXT: v_min_f32_e32 v2, 1.0, v2
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_negzero_maybe_snan_f32:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_mul_f32_e32 v2, 1.0, v3
|
|
; GFX8-NEXT: v_max_f32_e32 v2, 0x80000000, v2
|
|
; GFX8-NEXT: v_min_f32_e32 v2, 1.0, v2
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_negzero_maybe_snan_f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_max_f32_e32 v1, v1, v1
|
|
; GFX9-NEXT: v_max_f32_e32 v1, 0x80000000, v1
|
|
; GFX9-NEXT: v_min_f32_e32 v1, 1.0, v1
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_negzero_maybe_snan_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_max_f32_e32 v1, v1, v1
|
|
; GFX11-NEXT: v_maxmin_f32 v1, v1, 0x80000000, 1.0
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_negzero_maybe_snan_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1
|
|
; GFX12-NEXT: v_maxmin_num_f32 v1, v1, 0x80000000, 1.0
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%max = call float @llvm.maxnum.f32(float %a, float -0.0)
|
|
%med = call float @llvm.minnum.f32(float %max, float 1.0)
|
|
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_multi_use_max_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_multi_use_max_f32:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_mov_b32 s6, -1
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_mul_f32_e32 v2, 1.0, v2
|
|
; GFX6-NEXT: v_max_f32_e32 v2, 0, v2
|
|
; GFX6-NEXT: v_min_f32_e32 v3, 1.0, v2
|
|
; GFX6-NEXT: buffer_store_dword v3, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: buffer_store_dword v2, off, s[4:7], 0
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_multi_use_max_f32:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_mul_f32_e32 v2, 1.0, v3
|
|
; GFX8-NEXT: v_max_f32_e32 v2, 0, v2
|
|
; GFX8-NEXT: v_min_f32_e32 v3, 1.0, v2
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v3
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_multi_use_max_f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_max_f32_e32 v1, v1, v1
|
|
; GFX9-NEXT: v_max_f32_e32 v1, 0, v1
|
|
; GFX9-NEXT: v_min_f32_e32 v2, 1.0, v1
|
|
; GFX9-NEXT: global_store_dword v0, v2, s[4:5]
|
|
; GFX9-NEXT: global_store_dword v[0:1], v1, off
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_multi_use_max_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_max_f32_e32 v1, v1, v1
|
|
; GFX11-NEXT: v_max_f32_e32 v1, 0, v1
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_min_f32_e32 v2, 1.0, v1
|
|
; GFX11-NEXT: global_store_b32 v0, v2, s[0:1]
|
|
; GFX11-NEXT: global_store_b32 v[0:1], v1, off dlc
|
|
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_multi_use_max_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1
|
|
; GFX12-NEXT: v_max_num_f32_e32 v1, 0, v1
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_min_num_f32_e32 v2, 1.0, v1
|
|
; GFX12-NEXT: global_store_b32 v0, v2, s[0:1]
|
|
; GFX12-NEXT: s_wait_storecnt 0x0
|
|
; GFX12-NEXT: global_store_b32 v[0:1], v1, off scope:SCOPE_SYS
|
|
; GFX12-NEXT: s_wait_storecnt 0x0
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%max = call float @llvm.maxnum.f32(float %a, float 0.0)
|
|
%med = call float @llvm.minnum.f32(float %max, float 1.0)
|
|
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
store volatile float %max, ptr addrspace(1) undef
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_f16(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_f16:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_cvt_f32_f16_e64 v2, v2 clamp
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; GFX6-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_f16:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 1, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_ushort v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f16_e64 v2, v3, v3 clamp
|
|
; GFX8-NEXT: flat_store_short v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_f16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_ushort v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_max_f16_e64 v1, v1, v1 clamp
|
|
; GFX9-NEXT: global_store_short v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_f16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_u16 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_max_f16_e64 v1, v1, v1 clamp
|
|
; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_f16:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 1, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_u16 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f16_e64 v1, v1, v1 clamp
|
|
; GFX12-NEXT: global_store_b16 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid
|
|
%a = load half, ptr addrspace(1) %gep0
|
|
%max = call half @llvm.maxnum.f16(half %a, half 0.0)
|
|
%med = call half @llvm.minnum.f16(half %max, half 1.0)
|
|
|
|
store half %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_neg_f16(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_neg_f16:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_cvt_f32_f16_e64 v2, -v2 clamp
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; GFX6-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_neg_f16:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 1, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_ushort v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f16_e64 v2, -v3, -v3 clamp
|
|
; GFX8-NEXT: flat_store_short v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_neg_f16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_ushort v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_max_f16_e64 v1, -v1, -v1 clamp
|
|
; GFX9-NEXT: global_store_short v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_neg_f16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_u16 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_max_f16_e64 v1, -v1, -v1 clamp
|
|
; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_neg_f16:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 1, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_u16 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f16_e64 v1, -v1, -v1 clamp
|
|
; GFX12-NEXT: global_store_b16 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid
|
|
%a = load half, ptr addrspace(1) %gep0
|
|
%fneg.a = fneg half %a
|
|
%max = call half @llvm.maxnum.f16(half %fneg.a, half 0.0)
|
|
%med = call half @llvm.minnum.f16(half %max, half 1.0)
|
|
|
|
store half %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_negabs_f16(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_negabs_f16:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_cvt_f32_f16_e64 v2, -|v2| clamp
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; GFX6-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_negabs_f16:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 1, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_ushort v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f16_e64 v2, -|v3|, -|v3| clamp
|
|
; GFX8-NEXT: flat_store_short v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_negabs_f16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_ushort v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_max_f16_e64 v1, -|v1|, -|v1| clamp
|
|
; GFX9-NEXT: global_store_short v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_negabs_f16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_u16 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_max_f16_e64 v1, -|v1|, -|v1| clamp
|
|
; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_negabs_f16:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 1, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_u16 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f16_e64 v1, -|v1|, -|v1| clamp
|
|
; GFX12-NEXT: global_store_b16 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid
|
|
%a = load half, ptr addrspace(1) %gep0
|
|
%fabs.a = call half @llvm.fabs.f16(half %a)
|
|
%fneg.fabs.a = fneg half %fabs.a
|
|
|
|
%max = call half @llvm.maxnum.f16(half %fneg.fabs.a, half 0.0)
|
|
%med = call half @llvm.minnum.f16(half %max, half 1.0)
|
|
|
|
store half %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_f64(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_f64:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] clamp
|
|
; GFX6-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_f64:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v3, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] clamp
|
|
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_f64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 3, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dwordx2 v[0:1], v2, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] clamp
|
|
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_f64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] clamp
|
|
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_f64:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v2, 3, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b64 v[0:1], v2, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f64_e64 v[0:1], v[0:1], v[0:1] clamp
|
|
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr double, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr double, ptr addrspace(1) %out, i32 %tid
|
|
%a = load double, ptr addrspace(1) %gep0
|
|
%max = call double @llvm.maxnum.f64(double %a, double 0.0)
|
|
%med = call double @llvm.minnum.f64(double %max, double 1.0)
|
|
|
|
store double %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_neg_f64(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_neg_f64:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_max_f64 v[2:3], -v[2:3], -v[2:3] clamp
|
|
; GFX6-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_neg_f64:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v3, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f64 v[0:1], -v[0:1], -v[0:1] clamp
|
|
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_neg_f64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 3, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dwordx2 v[0:1], v2, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_max_f64 v[0:1], -v[0:1], -v[0:1] clamp
|
|
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_neg_f64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_max_f64 v[0:1], -v[0:1], -v[0:1] clamp
|
|
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_neg_f64:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v2, 3, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b64 v[0:1], v2, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f64_e64 v[0:1], -v[0:1], -v[0:1] clamp
|
|
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr double, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr double, ptr addrspace(1) %out, i32 %tid
|
|
%a = load double, ptr addrspace(1) %gep0
|
|
%fneg.a = fneg double %a
|
|
%max = call double @llvm.maxnum.f64(double %fneg.a, double 0.0)
|
|
%med = call double @llvm.minnum.f64(double %max, double 1.0)
|
|
|
|
store double %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_negabs_f64(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_negabs_f64:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_max_f64 v[2:3], -|v[2:3]|, -|v[2:3]| clamp
|
|
; GFX6-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_negabs_f64:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v3, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f64 v[0:1], -|v[0:1]|, -|v[0:1]| clamp
|
|
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_negabs_f64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 3, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dwordx2 v[0:1], v2, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_max_f64 v[0:1], -|v[0:1]|, -|v[0:1]| clamp
|
|
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_negabs_f64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_max_f64 v[0:1], -|v[0:1]|, -|v[0:1]| clamp
|
|
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_negabs_f64:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v2, 3, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b64 v[0:1], v2, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f64_e64 v[0:1], -|v[0:1]|, -|v[0:1]| clamp
|
|
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr double, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr double, ptr addrspace(1) %out, i32 %tid
|
|
%a = load double, ptr addrspace(1) %gep0
|
|
%fabs.a = call double @llvm.fabs.f64(double %a)
|
|
%fneg.fabs.a = fneg double %fabs.a
|
|
|
|
%max = call double @llvm.maxnum.f64(double %fneg.fabs.a, double 0.0)
|
|
%med = call double @llvm.minnum.f64(double %max, double 1.0)
|
|
|
|
store double %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_med3_aby_negzero_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_med3_aby_negzero_f32:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_brev_b32 s4, 1
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_med3_f32 v2, s4, 1.0, v2
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_med3_aby_negzero_f32:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: s_brev_b32 s0, 1
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_med3_f32 v2, s0, 1.0, v3
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_med3_aby_negzero_f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_brev_b32 s0, 1
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_med3_f32 v1, s0, 1.0, v1
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_med3_aby_negzero_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_med3_f32 v1, 0x80000000, 1.0, v1
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_med3_aby_negzero_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_med3_num_f32 v1, 0x80000000, 1.0, v1
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float -0.0, float 1.0, float %a)
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_med3_aby_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_med3_aby_f32:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_max_f32_e64 v2, v2, v2 clamp
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_med3_aby_f32:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f32_e64 v2, v3, v3 clamp
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_med3_aby_f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_max_f32_e64 v1, v1, v1 clamp
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_med3_aby_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_max_f32_e64 v1, v1, v1 clamp
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_med3_aby_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float 1.0, float %a)
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_med3_bay_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_med3_bay_f32:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_max_f32_e64 v2, v2, v2 clamp
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_med3_bay_f32:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f32_e64 v2, v3, v3 clamp
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_med3_bay_f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_max_f32_e64 v1, v1, v1 clamp
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_med3_bay_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_max_f32_e64 v1, v1, v1 clamp
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_med3_bay_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float 1.0, float 0.0, float %a)
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_med3_yab_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_med3_yab_f32:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_max_f32_e64 v2, v2, v2 clamp
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_med3_yab_f32:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f32_e64 v2, v3, v3 clamp
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_med3_yab_f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_max_f32_e64 v1, v1, v1 clamp
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_med3_yab_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_max_f32_e64 v1, v1, v1 clamp
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_med3_yab_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float %a, float 0.0, float 1.0)
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_med3_yba_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_med3_yba_f32:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_max_f32_e64 v2, v2, v2 clamp
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_med3_yba_f32:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f32_e64 v2, v3, v3 clamp
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_med3_yba_f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_max_f32_e64 v1, v1, v1 clamp
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_med3_yba_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_max_f32_e64 v1, v1, v1 clamp
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_med3_yba_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float %a, float 1.0, float 0.0)
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_med3_ayb_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_med3_ayb_f32:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_max_f32_e64 v2, v2, v2 clamp
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_med3_ayb_f32:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f32_e64 v2, v3, v3 clamp
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_med3_ayb_f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_max_f32_e64 v1, v1, v1 clamp
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_med3_ayb_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_max_f32_e64 v1, v1, v1 clamp
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_med3_ayb_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float %a, float 1.0)
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_med3_bya_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_med3_bya_f32:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_max_f32_e64 v2, v2, v2 clamp
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_med3_bya_f32:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f32_e64 v2, v3, v3 clamp
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_med3_bya_f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_max_f32_e64 v1, v1, v1 clamp
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_med3_bya_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_max_f32_e64 v1, v1, v1 clamp
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_med3_bya_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float 1.0, float %a, float 0.0)
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_constants_to_one_f32(ptr addrspace(1) %out) #0 {
|
|
; GFX6-LABEL: v_clamp_constants_to_one_f32:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: v_mov_b32_e32 v2, 1.0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_constants_to_one_f32:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX8-NEXT: v_mov_b32_e32 v2, 1.0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_constants_to_one_f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 1.0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_constants_to_one_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, 1.0 :: v_dual_and_b32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_constants_to_one_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
|
|
; GFX12-NEXT: v_dual_mov_b32 v1, 1.0 :: v_dual_and_b32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float 1.0, float 4.0)
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_constants_to_zero_f32(ptr addrspace(1) %out) #0 {
|
|
; GFX6-LABEL: v_clamp_constants_to_zero_f32:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: buffer_store_dword v1, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_constants_to_zero_f32:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX8-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_constants_to_zero_f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_constants_to_zero_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_constants_to_zero_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
|
|
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float 1.0, float -4.0)
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_constant_preserve_f32(ptr addrspace(1) %out) #0 {
|
|
; GFX6-LABEL: v_clamp_constant_preserve_f32:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: v_mov_b32_e32 v2, 0.5
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_constant_preserve_f32:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX8-NEXT: v_mov_b32_e32 v2, 0.5
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_constant_preserve_f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0.5
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_constant_preserve_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, 0.5 :: v_dual_and_b32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_constant_preserve_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
|
|
; GFX12-NEXT: v_dual_mov_b32 v1, 0.5 :: v_dual_and_b32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float 1.0, float 0.5)
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_constant_preserve_denorm_f32(ptr addrspace(1) %out) #0 {
|
|
; GFX6-LABEL: v_clamp_constant_preserve_denorm_f32:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: v_mov_b32_e32 v2, 0x7fffff
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_constant_preserve_denorm_f32:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fffff
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_constant_preserve_denorm_f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0x7fffff
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_constant_preserve_denorm_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, 0x7fffff :: v_dual_lshlrev_b32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_constant_preserve_denorm_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_dual_mov_b32 v1, 0x7fffff :: v_dual_lshlrev_b32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float 1.0, float bitcast (i32 8388607 to float))
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_constant_qnan_f32(ptr addrspace(1) %out) #0 {
|
|
; GFX6-LABEL: v_clamp_constant_qnan_f32:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: buffer_store_dword v1, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_constant_qnan_f32:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX8-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_constant_qnan_f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_constant_qnan_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_constant_qnan_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
|
|
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float 1.0, float 0x7FF8000000000000)
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_constant_snan_f32(ptr addrspace(1) %out) #0 {
|
|
; GFX6-LABEL: v_clamp_constant_snan_f32:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: buffer_store_dword v1, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_constant_snan_f32:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX8-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_constant_snan_f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_constant_snan_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_constant_snan_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
|
|
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float 1.0, float bitcast (i32 2139095041 to float))
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
; ---------------------------------------------------------------------
|
|
; Test non-default behaviors enabling snans and disabling dx10_clamp
|
|
; ---------------------------------------------------------------------
|
|
|
|
define amdgpu_kernel void @v_clamp_f32_no_dx10_clamp(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #2 {
|
|
; GFX6-LABEL: v_clamp_f32_no_dx10_clamp:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_add_f32_e32 v2, 0.5, v2
|
|
; GFX6-NEXT: v_med3_f32 v2, v2, 0, 1.0
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_f32_no_dx10_clamp:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_add_f32_e32 v2, 0.5, v3
|
|
; GFX8-NEXT: v_med3_f32 v2, v2, 0, 1.0
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_f32_no_dx10_clamp:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_f32_e32 v1, 0.5, v1
|
|
; GFX9-NEXT: v_med3_f32 v1, v1, 0, 1.0
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_f32_no_dx10_clamp:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_add_f32_e32 v1, 0.5, v1
|
|
; GFX11-NEXT: v_med3_f32 v1, v1, 0, 1.0
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_f32_no_dx10_clamp:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_add_f32_e64 v1, v1, 0.5 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%a.nnan = fadd nnan float %a, 0.5
|
|
%max = call float @llvm.maxnum.f32(float %a.nnan, float 0.0)
|
|
%med = call float @llvm.minnum.f32(float %max, float 1.0)
|
|
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_f32_snan_dx10clamp(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #3 {
|
|
; GFX6-LABEL: v_clamp_f32_snan_dx10clamp:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_add_f32_e64 v2, v2, 0.5 clamp
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_f32_snan_dx10clamp:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_add_f32_e64 v2, v3, 0.5 clamp
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_f32_snan_dx10clamp:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_f32_e64 v1, v1, 0.5 clamp
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_f32_snan_dx10clamp:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_add_f32_e64 v1, v1, 0.5 clamp
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_f32_snan_dx10clamp:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_add_f32_e64 v1, v1, 0.5 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%add = fadd float %a, 0.5
|
|
%max = call float @llvm.maxnum.f32(float %add, float 0.0)
|
|
%med = call float @llvm.minnum.f32(float %max, float 1.0)
|
|
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_f32_snan_no_dx10clamp(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #4 {
|
|
; GFX6-LABEL: v_clamp_f32_snan_no_dx10clamp:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_mul_f32_e32 v2, 1.0, v2
|
|
; GFX6-NEXT: v_med3_f32 v2, v2, 0, 1.0
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_f32_snan_no_dx10clamp:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_mul_f32_e32 v2, 1.0, v3
|
|
; GFX8-NEXT: v_med3_f32 v2, v2, 0, 1.0
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_f32_snan_no_dx10clamp:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_max_f32_e32 v1, v1, v1
|
|
; GFX9-NEXT: v_med3_f32 v1, v1, 0, 1.0
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_f32_snan_no_dx10clamp:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_max_f32_e32 v1, v1, v1
|
|
; GFX11-NEXT: v_med3_f32 v1, v1, 0, 1.0
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_f32_snan_no_dx10clamp:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%max = call float @llvm.maxnum.f32(float %a, float 0.0)
|
|
%med = call float @llvm.minnum.f32(float %max, float 1.0)
|
|
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_f32_snan_no_dx10clamp_nnan_src(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #4 {
|
|
; GFX6-LABEL: v_clamp_f32_snan_no_dx10clamp_nnan_src:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; GFX6-NEXT: v_med3_f32 v2, v2, 0, 1.0
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_f32_snan_no_dx10clamp_nnan_src:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_add_f32_e32 v2, 1.0, v3
|
|
; GFX8-NEXT: v_med3_f32 v2, v2, 0, 1.0
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_f32_snan_no_dx10clamp_nnan_src:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; GFX9-NEXT: v_med3_f32 v1, v1, 0, 1.0
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_f32_snan_no_dx10clamp_nnan_src:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; GFX11-NEXT: v_med3_f32 v1, v1, 0, 1.0
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_f32_snan_no_dx10clamp_nnan_src:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%add = fadd nnan float %a, 1.0
|
|
%max = call float @llvm.maxnum.f32(float %add, float 0.0)
|
|
%med = call float @llvm.minnum.f32(float %max, float 1.0)
|
|
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_med3_aby_f32_no_dx10_clamp(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #2 {
|
|
; GFX6-LABEL: v_clamp_med3_aby_f32_no_dx10_clamp:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_max_f32_e64 v2, v2, v2 clamp
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_med3_aby_f32_no_dx10_clamp:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f32_e64 v2, v3, v3 clamp
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_med3_aby_f32_no_dx10_clamp:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_max_f32_e64 v1, v1, v1 clamp
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_med3_aby_f32_no_dx10_clamp:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_max_f32_e64 v1, v1, v1 clamp
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_med3_aby_f32_no_dx10_clamp:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float 1.0, float %a)
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_med3_bay_f32_no_dx10_clamp(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #2 {
|
|
; GFX6-LABEL: v_clamp_med3_bay_f32_no_dx10_clamp:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_max_f32_e64 v2, v2, v2 clamp
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_med3_bay_f32_no_dx10_clamp:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f32_e64 v2, v3, v3 clamp
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_med3_bay_f32_no_dx10_clamp:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_max_f32_e64 v1, v1, v1 clamp
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_med3_bay_f32_no_dx10_clamp:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_max_f32_e64 v1, v1, v1 clamp
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_med3_bay_f32_no_dx10_clamp:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float 1.0, float 0.0, float %a)
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_med3_yab_f32_no_dx10_clamp(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #2 {
|
|
; GFX6-LABEL: v_clamp_med3_yab_f32_no_dx10_clamp:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_med3_f32 v2, v2, 0, 1.0
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_med3_yab_f32_no_dx10_clamp:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_med3_f32 v2, v3, 0, 1.0
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_med3_yab_f32_no_dx10_clamp:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_med3_f32 v1, v1, 0, 1.0
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_med3_yab_f32_no_dx10_clamp:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_med3_f32 v1, v1, 0, 1.0
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_med3_yab_f32_no_dx10_clamp:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float %a, float 0.0, float 1.0)
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_med3_yba_f32_no_dx10_clamp(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #2 {
|
|
; GFX6-LABEL: v_clamp_med3_yba_f32_no_dx10_clamp:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_med3_f32 v2, v2, 1.0, 0
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_med3_yba_f32_no_dx10_clamp:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_med3_f32 v2, v3, 1.0, 0
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_med3_yba_f32_no_dx10_clamp:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_med3_f32 v1, v1, 1.0, 0
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_med3_yba_f32_no_dx10_clamp:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_med3_f32 v1, v1, 1.0, 0
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_med3_yba_f32_no_dx10_clamp:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float %a, float 1.0, float 0.0)
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_med3_ayb_f32_no_dx10_clamp(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #2 {
|
|
; GFX6-LABEL: v_clamp_med3_ayb_f32_no_dx10_clamp:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_med3_f32 v2, 0, v2, 1.0
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_med3_ayb_f32_no_dx10_clamp:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_med3_f32 v2, 0, v3, 1.0
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_med3_ayb_f32_no_dx10_clamp:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_med3_f32 v1, 0, v1, 1.0
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_med3_ayb_f32_no_dx10_clamp:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_med3_f32 v1, 0, v1, 1.0
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_med3_ayb_f32_no_dx10_clamp:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float %a, float 1.0)
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_med3_bya_f32_no_dx10_clamp(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #2 {
|
|
; GFX6-LABEL: v_clamp_med3_bya_f32_no_dx10_clamp:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_med3_f32 v2, 1.0, v2, 0
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_med3_bya_f32_no_dx10_clamp:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_med3_f32 v2, 1.0, v3, 0
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_med3_bya_f32_no_dx10_clamp:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_med3_f32 v1, 1.0, v1, 0
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_med3_bya_f32_no_dx10_clamp:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_med3_f32 v1, 1.0, v1, 0
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_med3_bya_f32_no_dx10_clamp:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%a = load float, ptr addrspace(1) %gep0
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float 1.0, float %a, float 0.0)
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_constant_qnan_f32_no_dx10_clamp(ptr addrspace(1) %out) #2 {
|
|
; GFX6-LABEL: v_clamp_constant_qnan_f32_no_dx10_clamp:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: v_mov_b32_e32 v2, 0x7fc00000
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_constant_qnan_f32_no_dx10_clamp:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fc00000
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_constant_qnan_f32_no_dx10_clamp:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0x7fc00000
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_constant_qnan_f32_no_dx10_clamp:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, 0x7fc00000 :: v_dual_lshlrev_b32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_constant_qnan_f32_no_dx10_clamp:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
|
|
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float 1.0, float 0x7FF8000000000000)
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_constant_snan_f32_no_dx10_clamp(ptr addrspace(1) %out) #2 {
|
|
; GFX6-LABEL: v_clamp_constant_snan_f32_no_dx10_clamp:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: v_mov_b32_e32 v2, 0x7f800001
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_constant_snan_f32_no_dx10_clamp:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX8-NEXT: v_mov_b32_e32 v2, 0x7f800001
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_constant_snan_f32_no_dx10_clamp:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0x7f800001
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_constant_snan_f32_no_dx10_clamp:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, 0x7f800001 :: v_dual_lshlrev_b32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_constant_snan_f32_no_dx10_clamp:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
|
|
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
|
%med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float 1.0, float bitcast (i32 2139095041 to float))
|
|
store float %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_v2f16:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v2
|
|
; GFX6-NEXT: v_cvt_f32_f16_e64 v3, v3 clamp
|
|
; GFX6-NEXT: v_cvt_f32_f16_e64 v2, v2 clamp
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_v2f16:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f16_sdwa v2, v3, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
; GFX8-NEXT: v_max_f16_e64 v3, v3, v3 clamp
|
|
; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_v2f16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 clamp
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_v2f16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 clamp
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_v2f16:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
|
|
%a = load <2 x half>, ptr addrspace(1) %gep0
|
|
%max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> zeroinitializer)
|
|
%med = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half 1.0>)
|
|
|
|
store <2 x half> %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_v2f16_undef_elt(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_v2f16_undef_elt:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: v_mov_b32_e32 v4, 0x7fc00000
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v2
|
|
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
|
|
; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
|
|
; GFX6-NEXT: v_max_f32_e32 v2, 0x7fc00000, v2
|
|
; GFX6-NEXT: v_med3_f32 v3, v3, 0, v4
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; GFX6-NEXT: v_min_f32_e32 v2, 1.0, v2
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_v2f16_undef_elt:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: v_mov_b32_e32 v4, 0x7e00
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f16_sdwa v2, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
|
|
; GFX8-NEXT: v_max_f16_e32 v2, 0, v2
|
|
; GFX8-NEXT: v_max_f16_e32 v3, 0x7e00, v3
|
|
; GFX8-NEXT: v_min_f16_e32 v3, 1.0, v3
|
|
; GFX8-NEXT: v_min_f16_sdwa v2, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_v2f16_undef_elt:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 clamp
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_v2f16_undef_elt:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 clamp
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_v2f16_undef_elt:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
|
|
%a = load <2 x half>, ptr addrspace(1) %gep0
|
|
%max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> <half undef, half 0.0>)
|
|
%med = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half undef>)
|
|
|
|
store <2 x half> %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_v2f16_not_zero(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_v2f16_not_zero:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v2
|
|
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
|
|
; GFX6-NEXT: v_cvt_f32_f16_e64 v3, v3 clamp
|
|
; GFX6-NEXT: v_max_f32_e32 v2, 2.0, v2
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; GFX6-NEXT: v_min_f32_e32 v2, 1.0, v2
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_v2f16_not_zero:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f16_e32 v2, v3, v3
|
|
; GFX8-NEXT: v_max_f16_e32 v2, 2.0, v2
|
|
; GFX8-NEXT: v_max_f16_sdwa v3, v3, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
; GFX8-NEXT: v_min_f16_e32 v2, 1.0, v2
|
|
; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_v2f16_not_zero:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_pk_max_f16 v1, v1, v1
|
|
; GFX9-NEXT: v_pk_max_f16 v1, v1, 2.0
|
|
; GFX9-NEXT: v_pk_min_f16 v1, v1, 1.0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_v2f16_not_zero:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_pk_max_f16 v1, v1, v1
|
|
; GFX11-NEXT: v_pk_max_f16 v1, v1, 2.0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_pk_min_f16 v1, v1, 1.0 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_v2f16_not_zero:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
|
|
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, 2.0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, 1.0 op_sel_hi:[1,0]
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
|
|
%a = load <2 x half>, ptr addrspace(1) %gep0
|
|
%max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> <half 2.0, half 0.0>)
|
|
%med = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half 1.0>)
|
|
|
|
store <2 x half> %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_v2f16_not_one(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_v2f16_not_one:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v2
|
|
; GFX6-NEXT: v_cvt_f32_f16_e64 v3, v3 clamp
|
|
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; GFX6-NEXT: v_med3_f32 v2, v2, 0, 0
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_v2f16_not_one:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f16_e32 v2, v3, v3
|
|
; GFX8-NEXT: v_max_f16_e32 v2, 0, v2
|
|
; GFX8-NEXT: v_max_f16_sdwa v3, v3, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
; GFX8-NEXT: v_min_f16_e32 v2, 0, v2
|
|
; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_v2f16_not_one:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_pk_max_f16 v1, v1, v1
|
|
; GFX9-NEXT: v_pk_max_f16 v1, v1, 0
|
|
; GFX9-NEXT: v_pk_min_f16 v1, v1, 1.0 op_sel:[0,1] op_sel_hi:[1,0]
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_v2f16_not_one:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_pk_max_f16 v1, v1, v1
|
|
; GFX11-NEXT: v_pk_max_f16 v1, v1, 0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_pk_min_f16 v1, v1, 1.0 op_sel:[0,1] op_sel_hi:[1,0]
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_v2f16_not_one:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
|
|
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, 0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, 1.0 op_sel:[0,1] op_sel_hi:[1,0]
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
|
|
%a = load <2 x half>, ptr addrspace(1) %gep0
|
|
%max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> <half 0.0, half 0.0>)
|
|
%med = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 0.0, half 1.0>)
|
|
|
|
store <2 x half> %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_neg_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_neg_v2f16:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
|
|
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v2
|
|
; GFX6-NEXT: v_cvt_f32_f16_e64 v3, v3 clamp
|
|
; GFX6-NEXT: v_cvt_f32_f16_e64 v2, v2 clamp
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_neg_v2f16:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f16_sdwa v2, -v3, -v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
; GFX8-NEXT: v_max_f16_e64 v3, -v3, -v3 clamp
|
|
; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_neg_v2f16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 neg_lo:[1,1] neg_hi:[1,1] clamp
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_neg_v2f16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 neg_lo:[1,1] neg_hi:[1,1] clamp
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_neg_v2f16:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 neg_lo:[1,1] neg_hi:[1,1] clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
|
|
%a = load <2 x half>, ptr addrspace(1) %gep0
|
|
%fneg.a = fneg <2 x half> %a
|
|
%max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %fneg.a, <2 x half> zeroinitializer)
|
|
%med = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half 1.0>)
|
|
|
|
store <2 x half> %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_negabs_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_negabs_v2f16:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_or_b32_e32 v2, 0x80008000, v2
|
|
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v2
|
|
; GFX6-NEXT: v_cvt_f32_f16_e64 v3, v3 clamp
|
|
; GFX6-NEXT: v_cvt_f32_f16_e64 v2, v2 clamp
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_negabs_v2f16:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f16_sdwa v2, -|v3|, -|v3| clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
; GFX8-NEXT: v_max_f16_e64 v3, -|v3|, -|v3| clamp
|
|
; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_negabs_v2f16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v1
|
|
; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 neg_lo:[1,1] neg_hi:[1,1] clamp
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_negabs_v2f16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v1
|
|
; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 neg_lo:[1,1] neg_hi:[1,1] clamp
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_negabs_v2f16:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v1
|
|
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 neg_lo:[1,1] neg_hi:[1,1] clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
|
|
%a = load <2 x half>, ptr addrspace(1) %gep0
|
|
%fabs.a = call <2 x half> @llvm.fabs.v2f16(<2 x half> %a)
|
|
%fneg.fabs.a = fneg <2 x half> %fabs.a
|
|
|
|
%max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %fneg.fabs.a, <2 x half> zeroinitializer)
|
|
%med = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half 1.0>)
|
|
|
|
store <2 x half> %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_neglo_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_neglo_v2f16:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v2
|
|
; GFX6-NEXT: v_cvt_f32_f16_e64 v3, v3 clamp
|
|
; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX6-NEXT: v_cvt_f32_f16_e64 v2, -v2 clamp
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_neglo_v2f16:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f16_sdwa v2, v3, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
; GFX8-NEXT: v_max_f16_e64 v3, -v3, -v3 clamp
|
|
; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_neglo_v2f16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 neg_lo:[1,1] clamp
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_neglo_v2f16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 neg_lo:[1,1] clamp
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_neglo_v2f16:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 neg_lo:[1,1] clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
|
|
%a = load <2 x half>, ptr addrspace(1) %gep0
|
|
%lo = extractelement <2 x half> %a, i32 0
|
|
%neg.lo = fneg half %lo
|
|
%neg.lo.vec = insertelement <2 x half> %a, half %neg.lo, i32 0
|
|
%max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %neg.lo.vec, <2 x half> zeroinitializer)
|
|
%med = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half 1.0>)
|
|
|
|
store <2 x half> %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_neghi_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
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; GFX6-LABEL: v_clamp_neghi_v2f16:
|
|
; GFX6: ; %bb.0:
|
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; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
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; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
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; GFX6-NEXT: s_waitcnt vmcnt(0)
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; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v2
|
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; GFX6-NEXT: v_cvt_f32_f16_e64 v3, -v3 clamp
|
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; GFX6-NEXT: v_cvt_f32_f16_e64 v2, v2 clamp
|
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; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3
|
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; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
|
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; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
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; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
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; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_neghi_v2f16:
|
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; GFX8: ; %bb.0:
|
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; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
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; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
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; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
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; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
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; GFX8-NEXT: v_mov_b32_e32 v1, s1
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
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; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
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; GFX8-NEXT: s_waitcnt vmcnt(0)
|
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; GFX8-NEXT: v_max_f16_sdwa v2, -v3, -v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
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; GFX8-NEXT: v_max_f16_e64 v3, v3, v3 clamp
|
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; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
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; GFX8-NEXT: flat_store_dword v[0:1], v2
|
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; GFX8-NEXT: s_endpgm
|
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;
|
|
; GFX9-LABEL: v_clamp_neghi_v2f16:
|
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; GFX9: ; %bb.0:
|
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; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
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; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
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; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
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; GFX9-NEXT: s_waitcnt vmcnt(0)
|
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; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 neg_hi:[1,1] clamp
|
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; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
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; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_neghi_v2f16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 neg_hi:[1,1] clamp
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_neghi_v2f16:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 neg_hi:[1,1] clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
|
|
%a = load <2 x half>, ptr addrspace(1) %gep0
|
|
%hi = extractelement <2 x half> %a, i32 1
|
|
%neg.hi = fneg half %hi
|
|
%neg.hi.vec = insertelement <2 x half> %a, half %neg.hi, i32 1
|
|
%max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %neg.hi.vec, <2 x half> zeroinitializer)
|
|
%med = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half 1.0>)
|
|
|
|
store <2 x half> %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_v2f16_shuffle(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
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; GFX6-LABEL: v_clamp_v2f16_shuffle:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v2
|
|
; GFX6-NEXT: v_cvt_f32_f16_e64 v2, v2 clamp
|
|
; GFX6-NEXT: v_cvt_f32_f16_e64 v3, v3 clamp
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX6-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_v2f16_shuffle:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f16_sdwa v2, v3, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX8-NEXT: v_max_f16_sdwa v3, v3, v3 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_v2f16_shuffle:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 op_sel:[1,1] op_sel_hi:[0,0] clamp
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_v2f16_shuffle:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 op_sel:[1,1] op_sel_hi:[0,0] clamp
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_v2f16_shuffle:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 op_sel:[1,1] op_sel_hi:[0,0] clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
|
|
%a = load <2 x half>, ptr addrspace(1) %gep0
|
|
%shuf = shufflevector <2 x half> %a, <2 x half> undef, <2 x i32> <i32 1, i32 0>
|
|
%max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %shuf, <2 x half> zeroinitializer)
|
|
%med = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half 1.0>)
|
|
|
|
store <2 x half> %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_v2f16_undef_limit_elts0(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_v2f16_undef_limit_elts0:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: v_mov_b32_e32 v4, 0x7fc00000
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v2
|
|
; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
|
|
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
|
|
; GFX6-NEXT: v_max_f32_e32 v3, 0x7fc00000, v3
|
|
; GFX6-NEXT: v_min_f32_e32 v3, 1.0, v3
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; GFX6-NEXT: v_med3_f32 v2, v2, 0, v4
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_v2f16_undef_limit_elts0:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: v_mov_b32_e32 v4, 0x3c00
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f16_sdwa v2, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
|
|
; GFX8-NEXT: v_max_f16_e32 v2, 0x7e00, v2
|
|
; GFX8-NEXT: v_max_f16_e32 v3, 0, v3
|
|
; GFX8-NEXT: v_min_f16_e32 v3, 0x7e00, v3
|
|
; GFX8-NEXT: v_min_f16_sdwa v2, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_v2f16_undef_limit_elts0:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 clamp
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_v2f16_undef_limit_elts0:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 clamp
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_v2f16_undef_limit_elts0:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
|
|
%a = load <2 x half>, ptr addrspace(1) %gep0
|
|
%max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> <half 0.0, half undef>)
|
|
%med = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half undef, half 1.0>)
|
|
|
|
store <2 x half> %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_v2f16_undef_limit_elts1(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
|
|
; GFX6-LABEL: v_clamp_v2f16_undef_limit_elts1:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s6, 0
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
|
|
; GFX6-NEXT: v_mov_b32_e32 v4, 0x7fc00000
|
|
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v2
|
|
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
|
|
; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
|
|
; GFX6-NEXT: v_max_f32_e32 v2, 0x7fc00000, v2
|
|
; GFX6-NEXT: v_med3_f32 v3, v3, 0, v4
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; GFX6-NEXT: v_min_f32_e32 v2, 1.0, v2
|
|
; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_v2f16_undef_limit_elts1:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; GFX8-NEXT: v_mov_b32_e32 v4, 0x7e00
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v3, v[0:1]
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: v_max_f16_sdwa v2, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
|
|
; GFX8-NEXT: v_max_f16_e32 v2, 0, v2
|
|
; GFX8-NEXT: v_max_f16_e32 v3, 0x7e00, v3
|
|
; GFX8-NEXT: v_min_f16_e32 v3, 1.0, v3
|
|
; GFX8-NEXT: v_min_f16_sdwa v2, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_v2f16_undef_limit_elts1:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 clamp
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_v2f16_undef_limit_elts1:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 clamp
|
|
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_v2f16_undef_limit_elts1:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
|
|
%a = load <2 x half>, ptr addrspace(1) %gep0
|
|
%max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> <half undef, half 0.0>)
|
|
%med = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half undef>)
|
|
|
|
store <2 x half> %med, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_clamp_diff_source_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0
|
|
; GFX6-LABEL: v_clamp_diff_source_f32:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
|
|
; GFX6-NEXT: s_load_dword s2, s[2:3], 0x2
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: v_mov_b32_e32 v0, s5
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, s2
|
|
; GFX6-NEXT: v_add_f32_e32 v0, s4, v0
|
|
; GFX6-NEXT: v_add_f32_e32 v1, s4, v1
|
|
; GFX6-NEXT: v_max_f32_e64 v0, v0, v1 clamp
|
|
; GFX6-NEXT: s_mov_b32 s2, -1
|
|
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:12
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: v_clamp_diff_source_f32:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
|
|
; GFX8-NEXT: s_load_dword s2, s[2:3], 0x8
|
|
; GFX8-NEXT: s_add_u32 s0, s0, 12
|
|
; GFX8-NEXT: s_addc_u32 s1, s1, 0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v0, s5
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s2
|
|
; GFX8-NEXT: v_add_f32_e32 v0, s4, v0
|
|
; GFX8-NEXT: v_add_f32_e32 v1, s4, v1
|
|
; GFX8-NEXT: v_max_f32_e64 v2, v0, v1 clamp
|
|
; GFX8-NEXT: v_mov_b32_e32 v0, s0
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: v_clamp_diff_source_f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
|
|
; GFX9-NEXT: s_load_dword s2, s[6:7], 0x8
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s0, v1
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s0, v2
|
|
; GFX9-NEXT: v_max_f32_e64 v1, v1, v2 clamp
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[4:5] offset:12
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_clamp_diff_source_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX11-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: s_clause 0x1
|
|
; GFX11-NEXT: s_load_b64 s[4:5], s[2:3], 0x0
|
|
; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x8
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: v_add_f32_e64 v0, s4, s5
|
|
; GFX11-NEXT: v_add_f32_e64 v1, s4, s2
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_max_f32_e64 v0, v0, v1 clamp
|
|
; GFX11-NEXT: global_store_b32 v2, v0, s[0:1] offset:12
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_clamp_diff_source_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
|
|
; GFX12-NEXT: v_mov_b32_e32 v0, 0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: s_load_b96 s[4:6], s[2:3], 0x0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: s_add_f32 s2, s4, s5
|
|
; GFX12-NEXT: s_add_f32 s3, s4, s6
|
|
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3)
|
|
; GFX12-NEXT: s_max_num_f32 s2, s2, s3
|
|
; GFX12-NEXT: v_max_num_f32_e64 v1, s2, s2 clamp
|
|
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] offset:12
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
{
|
|
%gep1 = getelementptr float, ptr addrspace(1) %aptr, i32 1
|
|
%gep2 = getelementptr float, ptr addrspace(1) %aptr, i32 2
|
|
%l0 = load float, ptr addrspace(1) %aptr
|
|
%l1 = load float, ptr addrspace(1) %gep1
|
|
%l2 = load float, ptr addrspace(1) %gep2
|
|
%a = fadd nsz float %l0, %l1
|
|
%b = fadd nsz float %l0, %l2
|
|
%res = call nsz float @llvm.maxnum.f32(float %a, float %b)
|
|
%max = call nsz float @llvm.maxnum.f32(float %res, float 0.0)
|
|
%min = call nsz float @llvm.minnum.f32(float %max, float 1.0)
|
|
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 3
|
|
store float %min, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
declare i32 @llvm.amdgcn.workitem.id.x() #1
|
|
declare float @llvm.fabs.f32(float) #1
|
|
declare float @llvm.minnum.f32(float, float) #1
|
|
declare float @llvm.maxnum.f32(float, float) #1
|
|
declare float @llvm.amdgcn.fmed3.f32(float, float, float) #1
|
|
declare double @llvm.fabs.f64(double) #1
|
|
declare double @llvm.minnum.f64(double, double) #1
|
|
declare double @llvm.maxnum.f64(double, double) #1
|
|
declare half @llvm.fabs.f16(half) #1
|
|
declare half @llvm.minnum.f16(half, half) #1
|
|
declare half @llvm.maxnum.f16(half, half) #1
|
|
declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #1
|
|
declare <2 x half> @llvm.minnum.v2f16(<2 x half>, <2 x half>) #1
|
|
declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>) #1
|
|
|
|
attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
|
|
attributes #1 = { nounwind readnone }
|
|
attributes #2 = { nounwind "amdgpu-dx10-clamp"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-nans-fp-math"="false" }
|
|
attributes #3 = { nounwind "amdgpu-dx10-clamp"="true" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-nans-fp-math"="false" }
|
|
attributes #4 = { nounwind "amdgpu-dx10-clamp"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-nans-fp-math"="false" }
|