cdfd884b0e
Update TableGen specification of DXIL Op records in DXIL.td per the current design document. - Facilitate specification of overloads, shader stage and attributes predicated on DXIL Ops predicated DXIL version. Implement functionality to consume in TableGen backend, DXILEmitter, the above specification enhancements, and generate C++ code (in (DXILOperations.inc) that represents properties of DXIL Ops, associated type declarations and corresponding accessor functions. Changes to DXIL Op Lowering pass to consume the DXIL Op representation generated by the TableGen back end. Add mtriple with the required shader model version to commandline of tests.
26 lines
837 B
LLVM
26 lines
837 B
LLVM
; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s
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; Make sure dxil operation function calls for sin are generated for float and half.
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; CHECK:call float @dx.op.unary.f32(i32 13, float %{{.*}})
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; CHECK:call half @dx.op.unary.f16(i32 13, half %{{.*}})
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; Function Attrs: noinline nounwind optnone
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define noundef float @sin_float(float noundef %a) #0 {
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entry:
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%a.addr = alloca float, align 4
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store float %a, ptr %a.addr, align 4
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%0 = load float, ptr %a.addr, align 4
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%1 = call float @llvm.sin.f32(float %0)
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ret float %1
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}
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; Function Attrs: noinline nounwind optnone
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define noundef half @sin_half(half noundef %a) #0 {
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entry:
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%a.addr = alloca half, align 2
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store half %a, ptr %a.addr, align 2
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%0 = load half, ptr %a.addr, align 2
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%1 = call half @llvm.sin.f16(half %0)
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ret half %1
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}
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