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clang-p2996/llvm/test/CodeGen/RISCV
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Simon Pilgrim 7afdc6bd57 [DAG] Fix typo in i64/i128 abdu/abds tests 
I'd incorrectly swapped the operands in some of the "cmp" test patterns when I changed the condition code
2024-09-04 11:59:10 +01:00
..
GlobalISel
[RISCV][GISel] Use CCValAssign::getCustomReg for converting f16/f32<->GPR. (#105700)
2024-09-03 22:49:02 -07:00
intrinsics
…
rvv
[RISCV] Add passthru to vmv.v.v intrinsic tests. NFC
2024-09-04 13:51:32 +08:00
abds-neg.ll
[DAG] Fix typo in i64/i128 abdu/abds tests
2024-09-04 11:59:10 +01:00
abds.ll
[DAG] Fix typo in i64/i128 abdu/abds tests
2024-09-04 11:59:10 +01:00
abdu-neg.ll
[DAG] Fix typo in i64/i128 abdu/abds tests
2024-09-04 11:59:10 +01:00
abdu.ll
[DAG] Fix typo in i64/i128 abdu/abds tests
2024-09-04 11:59:10 +01:00
add-before-shl.ll
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add-imm.ll
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addc-adde-sube-subc.ll
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addcarry.ll
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addimm-mulimm.ll
[RISCV] Use RISCVISD::SHL_ADD in transformAddShlImm (#89832)
2024-05-13 09:48:46 -07:00
addrspacecast.ll
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aext-to-sext.ll
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aext.ll
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align-loops.ll
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align.ll
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alloca.ll
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allow-check.ll
[CodeGen] Add default lowering for llvm.allow.{runtime,ubsan}.check() (#86049)
2024-03-31 22:19:33 -07:00
alu8.ll
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alu16.ll
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alu32.ll
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alu64.ll
Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."
2024-04-29 13:08:52 +02:00
analyze-branch.ll
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and-add-lsr.ll
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and.ll
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arith-with-overflow.ll
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atomic-cmpxchg-branch-on-result.ll
[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)
2024-07-23 08:06:15 +01:00
atomic-cmpxchg-flag.ll
…
atomic-cmpxchg.ll
[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)
2024-07-23 08:06:15 +01:00
atomic-fence.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
atomic-load-store.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
atomic-rmw-discard.ll
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atomic-rmw-sub.ll
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atomic-rmw.ll
[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)
2024-07-23 08:06:15 +01:00
atomic-signext.ll
[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)
2024-07-23 08:06:15 +01:00
atomicrmw-uinc-udec-wrap.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
attributes-module-flag.ll
[RISCV] Make M imply Zmmul (#95070)
2024-06-21 11:11:10 +08:00
attributes.ll
[RISCV] Add CSRs and an instruction for Smctr and Ssctr extensions. (#105148)
2024-08-21 19:23:07 -07:00
avgceils.ll
[RISCV] Add scalar type test coverage for ISD::AVG nodes
2024-06-15 16:15:50 +01:00
avgceilu.ll
[RISCV] Add scalar type test coverage for ISD::AVG nodes
2024-06-15 16:15:50 +01:00
avgfloors.ll
[RISCV] Add scalar type test coverage for ISD::AVG nodes
2024-06-15 16:15:50 +01:00
avgflooru.ll
Recommit "[DAG] Reducing instructions by better legalization handling of AVGFLOORU for illegal data types" (#101223)
2024-07-30 19:00:46 -07:00
bf16-promote.ll
…
bfloat-arith.ll
[RISCV] Custom legalize f16/bf16 FCOPYSIGN with Zfhmin/Zbfmin. (#107039)
2024-09-02 22:04:09 -07:00
bfloat-br-fcmp.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-convert.ll
[RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel patterns that emit two instructions. (#107011)
2024-09-03 15:34:25 -07:00
bfloat-fcmp.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-frem.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-imm.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-isnan.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-mem.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-select-fcmp.ll
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
2024-09-03 16:04:51 -07:00
bfloat-select-icmp.ll
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
2024-09-03 16:04:51 -07:00
bfloat.ll
…
bitextract-mac.ll
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bitreverse-shift.ll
[DAG] Fold bitreverse(shl/srl(bitreverse(x),y)) -> srl/shl(x,y) (#89897)
2024-05-06 11:13:05 +01:00
bittest.ll
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blockaddress.ll
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branch_zero.ll
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branch-on-zero.ll
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branch-opt.ll
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branch-opt.mir
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branch-relaxation.ll
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branch.ll
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bswap-bitreverse.ll
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bswap-shift.ll
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byval.ll
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callee-saved-fpr32s.ll
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callee-saved-fpr64s.ll
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callee-saved-gprs.ll
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calling-conv-half.ll
[RISCV] Add constant folding combine for FMV_X_ANYEXTW/H. (#106653)
2024-08-30 09:43:42 -07:00
calling-conv-ilp32-ilp32f-common.ll
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calling-conv-ilp32-ilp32f-ilp32d-common.ll
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calling-conv-ilp32.ll
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calling-conv-ilp32d.ll
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calling-conv-ilp32e.ll
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calling-conv-ilp32f-ilp32d-common.ll
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calling-conv-lp64-lp64f-common.ll
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calling-conv-lp64-lp64f-lp64d-common.ll
[mi-sched] Suppress register pressure with i64. (#88256)
2024-04-15 13:11:45 +08:00
calling-conv-lp64.ll
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calling-conv-lp64e.ll
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calling-conv-rv32f-ilp32.ll
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calling-conv-rv32f-ilp32e.ll
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calling-conv-sext-zext.ll
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calling-conv-vector-float.ll
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calling-conv-vector-on-stack.ll
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calls.ll
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clear-cache.ll
[RISCV] Lower llvm.clear_cache to __riscv_flush_icache for glibc targets (#93481)
2024-06-20 07:27:07 +02:00
cm_mvas_mvsa.ll
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cm_mvas_mvsa.mir
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cmov-branch-opt.ll
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cmp-bool.ll
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codemodel-lowering.ll
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compress-double.ll
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compress-float.ll
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compress-inline-asm.ll
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compress-opt-branch.ll
[RISCV] Add Zca predicate to BrccCompressOpt patterns used for MinSize.
2024-04-05 12:39:39 -07:00
compress-opt-select.ll
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compress.ll
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condbinops.ll
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condops.ll
[RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891)
2024-07-27 17:26:32 -07:00
convert-highly-predictable-select-to-branch.ll
[RISCV] Add FeaturePredictableSelectIsExpensive
2024-07-05 11:29:42 +08:00
copy-frameindex.mir
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copyprop.ll
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copysign-casts.ll
[RISCV] Custom legalize f16/bf16 FCOPYSIGN with Zfhmin/Zbfmin. (#107039)
2024-09-02 22:04:09 -07:00
ctlz-cttz-ctpop.ll
[RISCV] Simplify (srl (and X, Mask), Const) to TH_EXTU (#102802)
2024-08-16 14:23:00 +08:00
ctz_zero_return_test.ll
Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)
2024-08-03 01:51:26 +03:00
disable-tail-calls.ll
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disjoint.ll
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div_minsize.ll
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div-by-constant.ll
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div-pow2.ll
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div.ll
[TargetLowering][AMDGPU][ARM][RISCV][X86] Teach SimplifyDemandedBits to combine (srl (sra X, C1), ShAmt) -> sra(X, C1+ShAmt) (#101751)
2024-08-14 08:44:57 -07:00
double_reduct.ll
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double-arith-strict.ll
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double-arith.ll
[RISCV][ISel] Fold FSGNJX idioms (#100718)
2024-07-27 12:51:58 +08:00
double-bitmanip-dagcombines.ll
DAG: Call SimplifyDemandedBits on fcopysign sign value (#97151)
2024-07-01 12:19:17 +02:00
double-br-fcmp.ll
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double-calling-conv.ll
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double-convert-strict.ll
[RISCV] Add some Zfinx instructions to hasAllNBitUsers.
2024-08-08 17:33:54 -07:00
double-convert.ll
[RISCV] Add some Zfinx instructions to hasAllNBitUsers.
2024-08-08 17:33:54 -07:00
double-fcmp-strict.ll
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double-fcmp.ll
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double-frem.ll
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double-imm.ll
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double-intrinsics-strict.ll
[clang] Reland Add tanf16 builtin and support for tan constrained intrinsic (#94559)
2024-06-10 20:46:26 -04:00
double-intrinsics.ll
RISC-V: Add fminimumnum and fmaximumnum support (#104411)
2024-08-21 09:10:55 +08:00
double-isnan.ll
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double-maximum-minimum.ll
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double-mem.ll
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double-previous-failure.ll
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double-round-conv-sat.ll
[DAGCombiner] Push freeze through SETCC and SELECT_CC (#64718)
2024-07-22 16:01:59 +02:00
double-round-conv.ll
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double-select-fcmp.ll
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double-select-icmp.ll
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double-stack-spill-restore.ll
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double-zfa.ll
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dso_local_equivalent.ll
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dwarf-eh.ll
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early-clobber-tied-def-subreg-liveness.ll
[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)
2024-08-31 19:28:36 +08:00
eh-dwarf-cfa.ll
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elf-preemption.ll
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emutls.ll
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exception-pointer-register.ll
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fastcc-float.ll
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fastcc-int.ll
[RISCV] Remove x7 from fastcc list. (#96729)
2024-07-17 08:37:55 +08:00
fastcc-without-f-reg.ll
[RISCV] Use XLenVT as LocVT for f16/f32/f164 with Zfinx in CC_RISCV_FastCC.
2024-08-26 16:34:12 -07:00
fixups-diff.ll
[MC] Rename temporary symbols of empty name to ".L0 " (#89693)
2024-04-26 08:30:27 -07:00
fli-licm.ll
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float-arith-strict.ll
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float-arith.ll
[RISCV][ISel] Fold FSGNJX idioms (#100718)
2024-07-27 12:51:58 +08:00
float-bit-preserving-dagcombines.ll
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float-bitmanip-dagcombines.ll
DAG: Call SimplifyDemandedBits on fcopysign sign value (#97151)
2024-07-01 12:19:17 +02:00
float-br-fcmp.ll
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float-convert-strict.ll
[RISCV] Add some Zfinx instructions to hasAllNBitUsers.
2024-08-08 17:33:54 -07:00
float-convert.ll
[RISCV] Add signext attribute to return of fmv_x_w test in float-convert.ll. NFC
2024-08-14 14:32:38 -07:00
float-fcmp-strict.ll
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float-fcmp.ll
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float-frem.ll
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float-imm.ll
[RISCV] Add constant folding combine for FMV_X_ANYEXTW/H. (#106653)
2024-08-30 09:43:42 -07:00
float-intrinsics-strict.ll
[RISCV] Correct the rounding mode for llvm.lround.i64.f32 with RV64+Zfinx.
2024-09-01 13:26:38 -07:00
float-intrinsics.ll
[RISCV] Correct the rounding mode for llvm.lround.i64.f32 with RV64+Zfinx.
2024-09-01 13:26:38 -07:00
float-isnan.ll
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float-maximum-minimum.ll
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float-mem.ll
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float-round-conv-sat.ll
Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."
2024-04-29 13:08:52 +02:00
float-round-conv.ll
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float-select-fcmp.ll
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float-select-icmp.ll
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float-select-verify.ll
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float-zfa.ll
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flt-rounds.ll
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fmax-fmin.ll
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fold-addi-loadstore.ll
[RISCV] Add a rematerializable pseudo instruction for LUI+ADDI for global addresses. (#93352)
2024-05-28 15:05:23 -07:00
fold-binop-into-select-return-constant.ll
[RISCV] Add a check in lowerSELECT after foldBinOpIntoSelectIfProfitable (#97391)
2024-07-05 10:55:36 +08:00
fold-binop-into-select.ll
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forced-atomics.ll
Reapply "[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)" (#90267)
2024-07-08 13:35:36 -07:00
fp16-promote.ll
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fp128.ll
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fpclamptosat.ll
Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."
2024-04-29 13:08:52 +02:00
fpenv.ll
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frame-info.ll
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frame.ll
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frameaddr-returnaddr.ll
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frm-dependency.ll
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get-register-invalid.ll
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get-register-noreserve.ll
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get-register-reserve.ll
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get-setcc-result-type.ll
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ghccc-nest.ll
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ghccc-rv32.ll
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ghccc-rv64.ll
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ghccc-without-f-reg.ll
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global-merge-minsize-smalldata-nonzero.ll
[GlobalMerge] Add MinSize feature to the GlobalMerge Pass. (#93686)
2024-06-03 09:10:56 -04:00
global-merge-minsize-smalldata-zero.ll
[GlobalMerge] Add MinSize feature to the GlobalMerge Pass. (#93686)
2024-06-03 09:10:56 -04:00
global-merge-minsize.ll
[GlobalMerge] Add MinSize feature to the GlobalMerge Pass. (#93686)
2024-06-03 09:10:56 -04:00
global-merge-offset.ll
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global-merge.ll
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graalcc.ll
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half-arith-strict.ll
[RISCV] Custom legalize f16/bf16 FNEG/FABS with Zfhmin/Zbfmin. (#106886)
2024-08-31 23:57:40 -07:00
half-arith.ll
[RISCV] Custom legalize f16/bf16 FCOPYSIGN with Zfhmin/Zbfmin. (#107039)
2024-09-02 22:04:09 -07:00
half-bitmanip-dagcombines.ll
[RISCV] Custom legalize f16/bf16 FCOPYSIGN with Zfhmin/Zbfmin. (#107039)
2024-09-02 22:04:09 -07:00
half-br-fcmp.ll
…
half-convert-strict.ll
[RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel patterns that emit two instructions. (#107011)
2024-09-03 15:34:25 -07:00
half-convert.ll
[RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel patterns that emit two instructions. (#107011)
2024-09-03 15:34:25 -07:00
half-fcmp-strict.ll
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half-fcmp.ll
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half-frem.ll
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half-imm.ll
[RISCV] Add constant folding combine for FMV_X_ANYEXTW/H. (#106653)
2024-08-30 09:43:42 -07:00
half-intrinsics.ll
[RISCV] Custom legalize f16/bf16 FCOPYSIGN with Zfhmin/Zbfmin. (#107039)
2024-09-02 22:04:09 -07:00
half-isnan.ll
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half-maximum-minimum.ll
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half-mem.ll
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half-round-conv-sat.ll
Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."
2024-04-29 13:08:52 +02:00
half-round-conv.ll
[RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel patterns that emit two instructions. (#107011)
2024-09-03 15:34:25 -07:00
half-select-fcmp.ll
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
2024-09-03 16:04:51 -07:00
half-select-icmp.ll
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
2024-09-03 16:04:51 -07:00
half-zfa-fli.ll
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half-zfa.ll
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hoist-global-addr-base.ll
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hwasan-check-memaccess.ll
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i32-icmp.ll
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i64-icmp.ll
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iabs.ll
Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."
2024-04-29 13:08:52 +02:00
idiv_large.ll
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imm-cse.ll
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imm.ll
[RISCV] Improve hasAllNBitUsers for users of SLLI.
2024-08-03 18:19:40 -07:00
indirectbr.ll
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init-array.ll
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inline-asm-abi-names.ll
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inline-asm-clobbers.ll
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inline-asm-d-abi-names.ll
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inline-asm-d-constraint-f.ll
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inline-asm-f-abi-names.ll
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inline-asm-f-constraint-f.ll
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inline-asm-i-constraint-i1.ll
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inline-asm-invalid.ll
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inline-asm-mem-constraint-2.ll
[test][RISCV] Precommit inline asm tests for #104925
2024-08-26 13:30:23 +03:00
inline-asm-mem-constraint.ll
[RISCV] Mark symbols used in inline asm for relocations as referenced (#104925)
2024-08-26 15:11:24 +03:00
inline-asm-s-constraint-error.ll
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inline-asm-s-constraint.ll
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inline-asm-zfh-constraint-f.ll
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inline-asm.ll
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inline-option-directive.ll
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interrupt-attr-args-error.ll
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interrupt-attr-callee.ll
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interrupt-attr-invalid.ll
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interrupt-attr-nocall.ll
[RISCV] Remove interrupt handler special case from RISCVFrameLowering::determineCalleeSaves. (#88069)
2024-04-10 10:28:54 -07:00
interrupt-attr-ret-error.ll
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interrupt-attr.ll
[RISCV] Remove interrupt handler special case from RISCVFrameLowering::determineCalleeSaves. (#88069)
2024-04-10 10:28:54 -07:00
intrinsic-cttz-elts-vscale.ll
[RISCV] Support postRA vsetvl insertion pass (#70549)
2024-05-21 14:42:55 +08:00
intrinsic-cttz-elts.ll
[RISCV] Provide a more efficient lowering for experimental.cttz.elts. (#88552)
2024-04-15 18:38:54 -07:00
isel-optnone.ll
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jumptable-swguarded.ll
[RISCV] Insert simple landing pad for taken address labels. (#91855)
2024-08-06 22:04:48 +08:00
jumptable.ll
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kcfi-isel-mir.ll
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kcfi-mir.ll
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kcfi-patchable-function-prefix.ll
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kcfi.ll
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lack-of-signed-truncation-check.ll
[RISCV] Select (and (sra x, c2), c1) as (srli (srai x, c2-c3), c3). (#101868)
2024-08-04 22:35:38 -07:00
large-stack.ll
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legalize-fneg.ll
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libcall-tail-calls.ll
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lit.local.cfg
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live-sp.mir
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llvm.exp10.ll
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llvm.frexp.ll
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load-setcc-combine.ll
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local-stack-slot-allocation.ll
[RISCV] Don't exlude the frame pointer from the callee saved registers in RISCVRegisterInfo::needsFrameBaseReg.
2024-05-13 12:58:30 -07:00
loop-strength-reduce-add-cheaper-than-mul.ll
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loop-strength-reduce-loop-invar.ll
[RISCV][LSR] Account for temporary register for base addition (#92296)
2024-05-22 13:38:39 -07:00
lpad.ll
[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)
2024-08-08 13:22:59 +08:00
lsr-legaladdimm.ll
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machine-combiner-mir.ll
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machine-combiner-strategies.ll
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machine-combiner.ll
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machine-combiner.mir
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machine-cp.mir
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machine-cse.ll
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machine-outliner-and-machine-copy-propagation.ll
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machine-outliner-cfi.mir
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machine-outliner-patchable.ll
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machine-outliner-position.mir
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machine-outliner-throw.ll
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machine-sink-load-immediate.ll
[MachineSink] Fix missing sinks along critical edges (#97618)
2024-07-09 10:48:22 -07:00
machinelicm-address-pseudos.ll
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machinelicm-constant-phys-reg.ll
[MachineLICM] Hoist copies of constant physical register (#93285)
2024-05-29 14:10:01 +08:00
machineoutliner-jumptable.mir
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machineoutliner-pcrel-lo.mir
[MachineOutliner] Leaf Descendants (#90275)
2024-06-18 07:13:05 -07:00
machineoutliner.mir
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MachineSink-implicit-x0.mir
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macro-fusion-lui-addi.ll
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macro-fusions.mir
…
make-compressible-for-store-address.mir
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make-compressible-rv64.mir
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make-compressible-zbc.mir
[RISCV] Teach RISCVMakeCompressible handle byte/half load/store for Zcb. (#83375)
2024-03-27 13:40:38 +08:00
make-compressible.mir
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mem64.ll
…
mem.ll
…
memcpy-inline.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
memcpy.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
memset-inline.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
min-max.ll
…
mir-target-flags.ll
…
misched-load-clustering.ll
…
misched-postra-direction.mir
[CodeGen][MISched] Add misched post-regalloc bidirectional scheduling (#77138)
2024-03-25 10:10:35 -04:00
miss-sp-restore-eh.ll
…
module-elf-flags.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
module-target-abi2.ll
…
module-target-abi3.ll
…
module-target-abi.ll
…
mul.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
musttail-call.ll
…
narrow-shl-cst.ll
…
neg-abs.ll
…
nest-register.ll
…
nomerge.ll
…
nontemporal-scalable.ll
…
nontemporal.ll
…
O0-pipeline.ll
[ExtendLifetimes] Implement llvm.fake.use to extend variable lifetimes (#86149)
2024-08-29 17:53:32 +01:00
O3-pipeline.ll
[ExtendLifetimes] Implement llvm.fake.use to extend variable lifetimes (#86149)
2024-08-29 17:53:32 +01:00
opt-w-instrs.mir
…
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax-relocation.ll
…
option-relax.ll
…
option-rvc.ll
…
optnone-store-no-combine.ll
…
or-is-add.ll
…
out-of-reach-emergency-slot.mir
…
overflow-intrinsic-optimizations.ll
…
overflow-intrinsics.ll
…
patchable-function-entry.ll
…
pei-crash.ll
…
pic-models.ll
…
pr40333.ll
…
pr51206.ll
…
pr53662.mir
…
pr55201.ll
…
pr56110.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
pr56457.ll
Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)
2024-08-03 01:51:26 +03:00
pr58025.ll
…
pr58286.ll
…
pr58511.ll
…
pr63365.ll
…
pr63816.ll
…
pr64503.ll
…
pr64645.ll
…
pr64772.ll
…
pr64935.ll
…
pr65025.ll
…
pr66603.ll
…
pr68855.ll
…
pr69586.ll
[RISCV] Support postRA vsetvl insertion pass (#70549)
2024-05-21 14:42:55 +08:00
pr80052.mir
…
pr84200.ll
…
pr84653_pr85190.ll
[DAGCombiner] Freeze maybe poison operands when folding select to logic (#84924)
2024-07-22 17:19:46 +02:00
pr88365.ll
[LLVM] [MC] Update frame layout & CFI generation to handle frames larger than 2gb (#99263)
2024-07-23 09:43:30 -07:00
pr90652.ll
[RISCV][ISel] Fix types in tryFoldSelectIntoOp (#90659)
2024-05-01 06:51:36 +08:00
pr90730.ll
[RISCV][ISel] Allow opaque constants in hasAndNotCompare (#92926)
2024-05-22 00:48:26 +08:00
pr92193.ll
[DAGCombiner] Mark vectors as not AllAddOne/AllSubOne on type mismatch (#92195)
2024-05-15 12:39:28 -07:00
pr94145.ll
[DAG] canCreateUndefOrPoison - fix missing argument typo
2024-06-02 10:34:48 +01:00
pr94265.ll
[RISCV] Replace hasStdExtV with hasVInstructions in isTruncateFree.
2024-07-29 17:15:02 -07:00
pr95271.ll
Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)
2024-08-03 01:51:26 +03:00
pr95284.ll
[DAG] combineShiftToAVG - don't create avgfloor with scalar constant operands unless legal.
2024-06-13 12:37:43 +01:00
pr96366.ll
[SDAG] Intersect poison-generating flags after CSE (#97434)
2024-07-03 20:32:46 +08:00
pr97304.ll
[RISCV] Copy call frame size when splitting basic block in emitSelectPseudo. (#99823)
2024-07-22 09:21:01 -07:00
prefer-w-inst.ll
[RISCV] Generate more W instructons
2024-04-16 15:37:31 +08:00
prefer-w-inst.mir
[RISCV] Generate more W instructons
2024-04-16 15:37:31 +08:00
prefetch.ll
…
prolog-epilogue.ll
[RISCV] Exploit sh3add/sh2add for stack offsets by shifted 12-bit constants (#87950)
2024-04-08 14:53:21 -07:00
push-pop-opt-crash.ll
…
push-pop-popret.ll
[RISCV] Add X27 to SavedRegs when X26 is in SavedRegs for cm.push/pop (#92067)
2024-05-14 08:06:10 -07:00
readcyclecounter.ll
…
readsteadycounter.ll
…
reduce-unnecessary-extension.ll
…
reduction-formation.ll
…
redundant-copy-from-tail-duplicate.ll
[RISCV][MCP] Remove redundant move from tail duplication (#89865)
2024-08-28 08:32:54 +08:00
regalloc-last-chance-recoloring-failure.ll
[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)
2024-08-31 19:28:36 +08:00
relax-per-target-feature.ll
…
rem.ll
…
remat.ll
…
renamable-copy.mir
[TII][RISCV] Add renamable bit to copyPhysReg (#91179)
2024-08-27 10:08:43 +08:00
repeated-fp-divisors.ll
…
reserved-reg-errors.ll
…
reserved-regs.ll
…
riscv-codegen-prepare-atp.ll
[RISCV] Implement RISCVTTIImpl::shouldConsiderAddressTypePromotion for RISCV (#102560)
2024-08-15 10:37:04 +08:00
riscv-codegenprepare-asm.ll
…
riscv-codegenprepare.ll
…
riscv-func-target-feature.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
riscv-shifted-extend.ll
…
riscv-tail-dup-size.ll
[RISCV] Increase default tail duplication threshold to 6 at -O3 (#98873)
2024-08-01 12:24:25 +08:00
rotl-rotr.ll
…
rv32-fuchsia.ll
…
rv32e.ll
…
rv32i-rv64i-float-double.ll
…
rv32i-rv64i-half.ll
…
rv32xtheadba.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
rv32xtheadbb.ll
Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)
2024-08-03 01:51:26 +03:00
rv32xtheadbs.ll
…
rv32zba.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
rv32zbb-intrinsic.ll
…
rv32zbb-zbkb.ll
…
rv32zbb.ll
Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)
2024-08-03 01:51:26 +03:00
rv32zbc-intrinsic.ll
…
rv32zbc-zbkc-intrinsic.ll
…
rv32zbkb-intrinsic.ll
…
rv32zbkb.ll
[RISCV] Support zext.h mnemonic with Zbkb. (#96821)
2024-06-27 09:31:26 -07:00
rv32zbkx-intrinsic.ll
…
rv32zbs.ll
…
rv32zimop-intrinsic.ll
[RISCV] Zimop/Zcmop are ratified
2024-04-08 16:40:02 +08:00
rv32zknd-intrinsic-autoupgrade.ll
…
rv32zknd-intrinsic.ll
…
rv32zkne-intrinsic-autoupgrade.ll
…
rv32zkne-intrinsic.ll
…
rv32zknh-intrinsic.ll
…
rv32zksed-intrinsic-autoupgrade.ll
…
rv32zksed-intrinsic.ll
…
rv32zksh-intrinsic.ll
…
rv64-large-stack.ll
…
rv64-patchpoint.ll
[RISCV] Implement Statepoint and Patchpoint lowering to call instructions (#77337)
2024-04-11 12:19:56 +08:00
rv64-stackmap-frame-setup.ll
…
rv64-stackmap-nops.ll
…
rv64-stackmap.ll
…
rv64-statepoint-call-lowering-x1.ll
[RISCV] Implement Statepoint and Patchpoint lowering to call instructions (#77337)
2024-04-11 12:19:56 +08:00
rv64-statepoint-call-lowering-x2.ll
[RISCV] Implement Statepoint and Patchpoint lowering to call instructions (#77337)
2024-04-11 12:19:56 +08:00
rv64-statepoint-call-lowering.ll
[RISCV] Implement Statepoint and Patchpoint lowering to call instructions (#77337)
2024-04-11 12:19:56 +08:00
rv64-typepromotion.ll
[RISCV][TypePromotion] Dont generate truncs if PromotedType is greater than Source Type (#86941)
2024-03-28 21:22:05 -07:00
rv64d-double-convert-strict.ll
…
rv64d-double-convert.ll
…
rv64e.ll
…
rv64f-float-convert-strict.ll
…
rv64f-float-convert.ll
…
rv64i-complex-float.ll
…
rv64i-demanded-bits.ll
[RISCV][ISel] Eliminate andi rd, rs1, -1 instructions (#89976)
2024-04-25 14:22:14 +08:00
rv64i-double-softfloat.ll
…
rv64i-exhaustive-w-insts.ll
…
rv64i-shift-sext.ll
…
rv64i-single-softfloat.ll
…
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
…
rv64m-exhaustive-w-insts.ll
…
rv64m-w-insts-legalization.ll
…
rv64xtheadba.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
rv64xtheadbb.ll
[RISCV] Simplify (srl (and X, Mask), Const) to TH_EXTU (#102802)
2024-08-16 14:23:00 +08:00
rv64xtheadbs.ll
…
rv64zba.ll
Recommit "[RISCV] Add isel optimization for (and (sra y, c2), c1) to recover regression from #101751. (#104114)"
2024-08-23 09:37:48 -07:00
rv64zbb-intrinsic.ll
…
rv64zbb-zbkb.ll
…
rv64zbb.ll
Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)
2024-08-03 01:51:26 +03:00
rv64zbc-intrinsic.ll
…
rv64zbc-zbkc-intrinsic.ll
…
rv64zbkb-intrinsic.ll
…
rv64zbkb.ll
[RISCV] Support zext.h mnemonic with Zbkb. (#96821)
2024-06-27 09:31:26 -07:00
rv64zbkx-intrinsic.ll
…
rv64zbs.ll
…
rv64zfh-half-convert-strict.ll
…
rv64zfh-half-convert.ll
[RISCV] Don't combine (sext_inreg (fmv_x_anyexth X), i16) with Zhinx.
2024-08-14 15:18:10 -07:00
rv64zfh-half-intrinsics.ll
…
rv64zfhmin-half-convert-strict.ll
[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)
2024-09-03 13:33:14 -07:00
rv64zfhmin-half-convert.ll
[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)
2024-09-03 13:33:14 -07:00
rv64zfhmin-half-intrinsics.ll
…
rv64zimop-intrinsic.ll
[RISCV] Zimop/Zcmop are ratified
2024-04-08 16:40:02 +08:00
rv64zknd-intrinsic.ll
…
rv64zknd-zkne-intrinsic.ll
…
rv64zkne-intrinsic.ll
…
rv64zknh-intrinsic-autoupgrade.ll
…
rv64zknh-intrinsic.ll
…
rv64zksed-intrinsic-autoupgrade2.ll
…
rv64zksed-intrinsic-autoupgrade.ll
…
rv64zksed-intrinsic.ll
…
rv64zksh-intrinsic-autoupgrade.ll
…
rv64zksh-intrinsic.ll
…
rvv-cfi-info.ll
[RISCV][CFI] Emit cfi_offset for every callee-saved vector registers (#100455)
2024-07-29 11:03:07 +08:00
sadd_sat_plus.ll
…
sadd_sat.ll
…
saverestore-scs.ll
…
saverestore.ll
…
scmp.ll
[SelectionDAG] Expand [US]CMP using arithmetic on boolean values instead of selects (#98774)
2024-07-16 20:56:18 +01:00
sdata-limit-0.ll
…
sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
…
sdata-sections.ll
[RISCV] Let -data-sections also work on sbss/sdata sections (#87040)
2024-08-23 14:06:12 +01:00
sdiv-pow2-cmov.ll
…
select-and.ll
…
select-bare.ll
…
select-binop-identity.ll
…
select-cc.ll
…
select-const.ll
…
select-constant-xor.ll
…
select-optimize-multiple.ll
…
select-optimize-multiple.mir
[NewPM][CodeGen] Port finalize-isel to new pass manager (#94214)
2024-06-04 09:23:52 +08:00
select-or.ll
…
select-to-and-zext.ll
…
select.ll
[RISC-V][ISel] Remove redundant czero.eqz like 'czero.eqz a0, a0, a0' (#90208)
2024-04-28 13:28:14 +08:00
selectcc-to-shiftand.ll
[RISCV] Limit (and (sra x, c2), c1) -> (srli (srai x, c2-c3), c3) isel in some cases. (#102034)
2024-08-06 20:27:14 -07:00
setcc-logic.ll
…
sext-zext-trunc.ll
…
sextw-removal-debug.mir
…
sextw-removal.ll
Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)
2024-08-03 01:51:26 +03:00
shadowcallstack.ll
…
shift-amount-mod.ll
…
shift-and.ll
…
shift-masked-shamt.ll
…
shifts.ll
…
shl-cttz.ll
[RISCV] Remove riscv-experimental-rv64-legal-i32. (#102509)
2024-08-09 11:48:48 -07:00
shl-demanded.ll
…
shlimm-addimm.ll
…
short-forward-branch-opt.ll
…
shrinkwrap-jump-table.ll
…
shrinkwrap.ll
…
sifive7-enable-intervals.mir
…
signbit-test.ll
…
signed-truncation-check.ll
[RISCV] Select (and (sra x, c2), c1) as (srli (srai x, c2-c3), c3). (#101868)
2024-08-04 22:35:38 -07:00
sink-and-fold-crash.mir
[MachineSink][RISCV] Only call isConstantPhysReg or isIgnorableUse for uses. (#99363)
2024-07-17 13:06:58 -07:00
sink-icmp.ll
…
spill-fill-fold.ll
…
spill-fpr-scalar.ll
[RISCV] Rewrite spill-fpr-scalar.ll test to not use vsetvli. NFC (#91428)
2024-05-08 11:33:05 +08:00
spir-kernel-cc.ll
…
split-offsets.ll
…
split-sp-adjust.ll
…
split-store.ll
…
split-udiv-by-constant.ll
…
split-urem-by-constant.ll
…
srem-lkk.ll
…
srem-seteq-illegal-types.ll
[TargetLowering][AMDGPU][ARM][RISCV][X86] Teach SimplifyDemandedBits to combine (srl (sra X, C1), ShAmt) -> sra(X, C1+ShAmt) (#101751)
2024-08-14 08:44:57 -07:00
srem-vector-lkk.ll
…
srodata.ll
…
ssub_sat_plus.ll
…
ssub_sat.ll
…
stack-folding.ll
…
stack-inst-compress.mir
…
stack-offset.ll
[RISCV] Exploit sh3add/sh2add for stack offsets by shifted 12-bit constants (#87950)
2024-04-08 14:53:21 -07:00
stack-protector-target.ll
[RISCV] Use the thread local stack protector for Android targets (#87672)
2024-05-13 08:52:59 -07:00
stack-realignment-with-variable-sized-objects.ll
…
stack-realignment.ll
…
stack-slot-coloring.mir
…
stack-slot-size.ll
…
stack-store-check.ll
…
subtarget-features-std-ext.ll
…
switch-width.ll
…
tagged-globals.ll
…
tail-calls.ll
[RISCV] Add a rematerializable pseudo instruction for LUI+ADDI for global addresses. (#93352)
2024-05-28 15:05:23 -07:00
target-abi-invalid.ll
…
target-abi-valid.ll
…
thread-pointer.ll
…
tls-models.ll
…
tlsdesc-symbol.ll
…
trunc-free.ll
…
typepromotion-overflow.ll
…
uadd_sat_plus.ll
[LegalizeTypes][RISCV] Use signed promotion for UADDSAT if that's what the target prefers. (#102842)
2024-08-12 09:34:51 -07:00
uadd_sat.ll
…
ucmp.ll
[LegalizeTypes][RISCV][LoongArch] Optimize promotion of ucmp. (#101366)
2024-07-31 17:18:27 -07:00
umulo-128-legalisation-lowering.ll
…
unaligned-load-store.ll
[RISCV] Improve constant materialisation for stores of i8 negative constants (#92131)
2024-05-14 19:08:04 +01:00
unfold-masked-merge-scalar-variablemask.ll
…
unroll-loop-cse.ll
[RISCV] Add a rematerializable pseudo instruction for LUI+ADDI for global addresses. (#93352)
2024-05-28 15:05:23 -07:00
urem-lkk.ll
…
urem-seteq-illegal-types.ll
…
urem-vector-lkk.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
usub_sat_plus.ll
[LegalizeTypes][RISCV] Use SExtOrZExtPromotedOperands to promote operands for USUBSAT. (#102781)
2024-08-11 10:22:31 -07:00
usub_sat.ll
…
vararg-ilp32e.ll
…
vararg.ll
…
vector-abi.ll
…
verify-instr.mir
[CodeGen][NewPM] Port MachineVerifier to new pass manager (#98628)
2024-07-15 12:42:44 +08:00
vlenb.ll
[MachineLICM] Hoist copies of constant physical register (#93285)
2024-05-29 14:10:01 +08:00
vscale-demanded-bits.ll
Move stepvector intrinsic out of experimental namespace (#98043)
2024-08-28 12:48:20 +01:00
wide-mem.ll
…
wide-scalar-shift-by-byte-multiple-legalization.ll
…
wide-scalar-shift-legalization.ll
…
xaluo.ll
[RISCV] Use SHL_ADD in remaining strength reduce cases for MUL (#89789)
2024-04-23 12:40:55 -07:00
xcvalu.ll
[RISCV] Implement Intrinsics Support for XCValu Extension in CV32E40P (#85603)
2024-07-04 01:25:10 +10:00
xcvbi.ll
[RISCV] Codegen support for XCVbi extension (#89719)
2024-05-08 11:22:16 +08:00
xcvbitmanip.ll
…
xcvmac.ll
[RISCV] Implement Intrinsics for XCVmac Extension in CV32E40P (#83112)
2024-07-15 10:25:25 +10:00
xcvmem.ll
[RISCV] Codegen support for XCVmem extension (#76916)
2024-06-07 21:45:49 +08:00
xtheadfmemidx.ll
…
xtheadmac.ll
…
xtheadmemidx.ll
…
xtheadmempair.ll
…
zbb-cmp-combine.ll
…
zcb-regalloc-hints.ll
…
zcmp-additional-stack.ll
[RISCV] Align stack size down to a multiple of 16 before using cm.push/pop. (#86073)
2024-03-26 21:37:19 -07:00
zcmp-cm-popretz.mir
…
zcmp-cm-push-pop.mir
…
zcmp-prolog-epilog-crash.mir
…
zcmp-with-float.ll
…
zdinx-asm-constraint.ll
…
zdinx-boundary-check.ll
[RISCV] Fix more boundary cases in immediate selection for Zdinx load/store on RV32. (#105874)
2024-08-25 14:27:08 -07:00
zdinx-large-spill.mir
[RISCV] Preserve MMO when expanding PseudoRV32ZdinxSD/PseudoRV32ZdinxLD. (#85877)
2024-03-26 20:42:14 -07:00
zext-with-load-is-free.ll
…
zfh-half-intrinsics-strict.ll
…
zfh-half-intrinsics.ll
…
zfhmin-half-intrinsics-strict.ll
…
zfhmin-half-intrinsics.ll
[RISCV] Add test for llvm.round.i32.f16 RV64+Zfhmin/Zhinxmin. NFC
2024-09-01 12:15:00 -07:00
zfhmin-imm.ll
…
zicfilp-indirect-branch.ll
[RISCV] Avoid using x7/t2 for indirect branches which need landing pad. (#68292)
2024-05-02 10:32:40 +08:00
zmmul.ll
…