6f92339d9e
Add a version of calculateRegisterUsage that works estimates register usage for a VPlan. This mostly just ports the existing code, with some updates to figure out what recipes will generate vectors vs scalars. There are number of changes in the computed register usages, but they should be more accurate w.r.t. to the generated vector code. There are the following changes: * Scalar usage increases in most cases by 1, as we always create a scalar canonical IV, which is alive across the loop and is not considered by the legacy implementation * Output is ordered by insertion, now scalar registers are added first due the canonical IV phi. * Using the VPlan, we now also more precisely know if an induction will be vectorized or scalarized. Depends on https://github.com/llvm/llvm-project/pull/126415 PR: https://github.com/llvm/llvm-project/pull/126437
47 lines
2.3 KiB
LLVM
47 lines
2.3 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt --passes=loop-vectorize --mtriple loongarch64-linux-gnu \
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; RUN: --mattr=+lsx -debug-only=loop-vectorize --force-vector-width=1 \
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; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-SCALAR
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; RUN: opt --passes=loop-vectorize --mtriple loongarch64-linux-gnu \
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; RUN: --mattr=+lsx -debug-only=loop-vectorize --force-vector-width=4 \
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; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-VECTOR
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define void @bar(ptr %A, i32 signext %n) {
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; CHECK-LABEL: bar
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; CHECK-SCALAR: LV(REG): Found max usage: 2 item
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; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: LoongArch::GPRRC, 3 registers
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; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: LoongArch::FPRRC, 1 registers
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; CHECK-SCALAR-NEXT: LV(REG): Found invariant usage: 1 item
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; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: LoongArch::GPRRC, 1 registers
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; CHECK-SCALAR-NEXT: LV: The target has 30 registers of LoongArch::GPRRC register class
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; CHECK-SCALAR-NEXT: LV: The target has 32 registers of LoongArch::FPRRC register class
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; CHECK-VECTOR: LV(REG): Found max usage: 2 item
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; CHECK-VECTOR-NEXT: LV(REG): RegisterClass: LoongArch::GPRRC, 2 registers
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; CHECK-VECTOR-NEXT: LV(REG): RegisterClass: LoongArch::VRRC, 2 registers
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; CHECK-VECTOR-NEXT: LV(REG): Found invariant usage: 1 item
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; CHECK-VECTOR-NEXT: LV(REG): RegisterClass: LoongArch::GPRRC, 1 registers
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; CHECK-VECTOR-NEXT: LV: The target has 30 registers of LoongArch::GPRRC register class
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; CHECK-VECTOR-NEXT: LV: The target has 32 registers of LoongArch::VRRC register class
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entry:
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%cmp4 = icmp sgt i32 %n, 0
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br i1 %cmp4, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader: ; preds = %entry
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%wide.trip.count = zext nneg i32 %n to i64
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br label %for.body
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for.cond.cleanup: ; preds = %for.body, %entry
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ret void
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for.body: ; preds = %for.body.preheader, %for.body
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%indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ]
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%0 = trunc i64 %indvars.iv to i32
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%conv = sitofp i32 %0 to float
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%arrayidx = getelementptr inbounds float, ptr %A, i64 %indvars.iv
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store float %conv, ptr %arrayidx, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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}
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