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clang-p2996/llvm/test/Transforms/SLPVectorizer
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Alexey Bataev 4aca20c8b6 [SLP]Pre-cache the last instruction for all entries before vectorization 
Need to pre-cache last instruction to avoid unexpected changes in the
last instruction detection during the vectorization, caused by adding
the new vector instructions, which add new uses and may affect the
analysis.
2025-04-16 11:44:55 -07:00
..
AArch64
[SLP] Make getSameOpcode support interchangeable instructions. (#135797)
2025-04-16 00:08:59 +08:00
AMDGPU
[SLP] Sort PHIs by ExtractElements when relevant (#131229)
2025-03-17 14:19:46 -07:00
ARM
[SLP]Check the MainOp matches the requirements for the instructions
2025-01-28 06:00:52 -08:00
NVPTX
[NVPTX] Customize getScalarizationOverhead (#128077)
2025-03-29 01:31:33 +00:00
PowerPC
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RISCV
[SLP]Fix type promotion for smax reduction with unsigned reduced operands
2025-04-16 10:14:29 -07:00
SystemZ
[SLP][REVEC] VectorValuesAndScales should be supported by REVEC. (#135762)
2025-04-15 23:03:55 +08:00
VE
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WebAssembly
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X86
[SLP]Pre-cache the last instruction for all entries before vectorization
2025-04-16 11:44:55 -07:00
XCore
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abs-overflow-incorrect-minbws.ll
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addsub.ll
[SLP]Reduce number of alternate instruction, where possible
2025-03-12 08:18:51 -07:00
alt-cmp-vectorize.ll
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alternate-cmp-swapped-pred-parent.ll
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alternate-non-profitable.ll
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alternate-opcode-sindle-bv.ll
[SLP] Make getSameOpcode support interchangeable instructions. (#135797)
2025-04-16 00:08:59 +08:00
arith-div-undef.ll
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bbi-106161.ll
[SLP] Make getSameOpcode support interchangeable instructions. (#135797)
2025-04-16 00:08:59 +08:00
bool-logical-op-reduction-with-poison.ll
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buildvector-insert-mask-size.ll
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buildvector-nodes-dependency.ll
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call-arg-reduced-by-minbitwidth.ll
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catchswitch.ll
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consecutive-access.ll
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const-bool-logical-or-reduction.ll
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crash_exceed_scheduling.ll
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crash_extractelement_poison.ll
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diamond_broadcast.ll
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empty-struct.ll
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ext-after-phi-node.ll
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ext-int-reduced-not-operand.ll
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extended-vectorized-gathered-inst.ll
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external-user-instruction-minbitwidth.ll
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extract_with_non_const_index.ll
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extract-many-users-buildvector.ll
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extract-subvector-long-input.ll
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extract-vectorized-operand.ll
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extractelement-insertpoint.ll
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extractlements-gathered-first-node.ll
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extracts-with-undefs.ll
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fix-113880.ll
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freeze-signedness-missed.ll
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full-overlap-non-schedulable.ll
[SLP]Synchronize cost of gather/buildvector nodes with codegen
2025-04-11 09:42:34 -04:00
gather_extract_from_vectorbuild.ll
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gathered-consecutive-loads-different-types.ll
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gep-with-extractelement-many-users.ll
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icmp-altopcode-after-reordering.ll
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insert-crash-index.ll
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insert-element-build-vector-const.ll
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insert-element-build-vector-inseltpoison.ll
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insert-element-build-vector.ll
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insert-element-multiple-uses.ll
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insert-shuffle.ll
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insertelement-across-zero.ll
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insertelement-postpone.ll
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insertelement-uses-vectorized-index.ll
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InstructionsState-is-invalid-2.ll
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int_sideeffect.ll
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int-bitcast-minbitwidth.ll
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is_fpclass.ll
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isOpcodeOrAlt.ll
[SLP] Make getSameOpcode support interchangeable instructions. (#135797)
2025-04-16 00:08:59 +08:00
jumbled_store_crash.ll
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limit.ll
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logical-ops-poisonous-repeated.ll
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materialize-vector-of-consts.ll
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minbitwidth-multiuse-with-insertelement.ll
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minbitwidth-node-with-multi-users.ll
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minbitwidth-user-not-min.ll
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multi-node-vectorized-insts.ll
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multi-uses-with-deps-in-first.ll
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one-element-vector.ll
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operand-is-reduced-val.ll
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orig-btiwidth-les-projected.ll
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partial-register-extract.ll
[SLP]Improved reduction cost/codegen
2025-02-14 11:03:33 -08:00
peek-through-shuffle.ll
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phi-node-bitwidt-op-not.ll
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phi-not-ordered.ll
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phi-undef-input.ll
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postponed_gathers.ll
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pr31599-inseltpoison.ll
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pr31599.ll
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rdar128092379.ll
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reduced-gathered-vectorized.ll
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reduction_loads.ll
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reduction-gather-non-scheduled-extracts.ll
[SLP]Use TTI::getScalarizationOverhead where possible
2025-02-04 18:49:43 -05:00
reduction-min-select.ll
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reduction-modified-values.ll
[SLP]Improved reduction cost/codegen
2025-02-14 11:03:33 -08:00
reduction-whole-regs-loads.ll
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reorder-clustered-node.ll
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reorder-node.ll
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reordered-top-scalars.ll
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reordering-single-phi.ll
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reschedule.ll
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resized-alt-shuffle-after-minbw.ll
[SLP] Make getSameOpcode support interchangeable instructions. (#135797)
2025-04-16 00:08:59 +08:00
return.ll
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reudction-or-non-poisoned.ll
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reused-buildvector-matching-vectorized-node.ll
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reused-scalar-in-multi-node.ll
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revec-fix-109835.ll
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revec-reduction-logical.ll
[SLP]Fix same/alternate analysis in split node analysis for compares
2025-03-31 19:33:40 -04:00
revec-shufflevector.ll
[SLP][REVEC] Fix ShuffleVector does not consider alternate instruction. (#134599)
2025-04-08 08:04:43 +08:00
revec.ll
[SLP][REVEC] getNumElements should not be used as VF when REVEC is enabled. (#134763)
2025-04-08 22:29:03 +08:00
root-trunc-extract-reuse.ll
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same-scalar-in-same-phi-extract.ll
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same-scalars-reordered-in-reduction.ll
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scalarazied-result.ll
[SLP]Use TTI::getScalarizationOverhead where possible
2025-02-04 18:49:43 -05:00
scalarization-overhead.ll
[SLP]Improved reduction cost/codegen
2025-02-14 11:03:33 -08:00
several_store_chains.ll
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shrink_after_reorder2.ll
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shuffle-mask-resized.ll
[SLP] Make getSameOpcode support interchangeable instructions. (#135797)
2025-04-16 00:08:59 +08:00
shuffle-multivector.ll
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shufflebuilder-bug.ll
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slp-deleted-inst.ll
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slp-hr-with-reuse.ll
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slp-max-phi-size.ll
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slp-max-reg-size.ll
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slp-non-pow-2-insertelement.ll
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slp-umax-rdx-matcher-crash.ll
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slp-variable-insertelement.ll
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splat-buildvector.ll
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stores-non-ordered.ll
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unknown-entries.ll
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vectorizable-functions-inseltpoison.ll
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vectorizable-functions.ll
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vectorize-reorder-alt-shuffle.ll
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vectorize-reordered-list.ll
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zext-incoming-for-neg-icmp.ll
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