Muzammil c409da2223 [mlir][ROCDL] Add permlanex16 op to allow subgroup reductions on gfx10+ (#135983) ...

Adding Permlanex16Op to ROCDL dialect to enable subgroup reduce lowering
to DPP ops for gfx 10+ devices.
See [this PR](https://github.com/llvm/llvm-project/pull/133204).

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Signed-off-by: Muzammiluddin Syed <muzasyed@amd.com>

2025-04-16 16:53:17 -05:00

..

Cpp

[MLIR][EmitC][cf] Bugfix: correctly inline emitc.expression op in the emitted if condition of a cf.cond_br (#128958)

2025-02-28 15:00:16 +01:00

LLVMIR

[mlir][ROCDL] Add permlanex16 op to allow subgroup reductions on gfx10+ (#135983)

2025-04-16 16:53:17 -05:00

SMTLIB

[mlir][SMT] add export smtlib (#131492)

2025-04-12 16:39:16 -04:00

SPIRV

[mlir][spirv] Allow yielding values from selection regions (#133702)

2025-04-02 14:35:22 +01:00