Carl Ritson 78ab7adbd3 [AMDGPU] Pre-commit test for D124981. NFC.

2022-05-10 09:48:25 +09:00

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AArch64

[AArch64][SVE] Improve codegen when extracting first lane of active lane mask

2022-05-09 13:56:04 +01:00

AMDGPU

[AMDGPU] Pre-commit test for D124981. NFC.

2022-05-10 09:48:25 +09:00

ARC

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ARM

[DAG] Prevent infinite loop combining bitcast shuffle

2022-05-09 09:36:22 +01:00

AVR

[AVR] Always expand STDSPQRr & STDWSPQRr

2022-05-05 03:10:59 +00:00

BPF

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CSKY

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DirectX

Modify DXILPrepare to emit no-op bitcasts

2022-05-09 13:40:47 -05:00

Generic

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Hexagon

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Inputs

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Lanai

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LoongArch

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M68k

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Mips

[SelectionDAG] Clear promoted bits before UREM on shift amount in PromoteIntRes_FunnelShift.

2022-05-06 09:26:30 -07:00

MIR

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MLRegalloc

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MSP430

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NVPTX

[NVPTX] Prefix "$L__" for branch label names

2022-04-30 21:55:20 +02:00

PowerPC

[DAGCombine] Add node in the worklist in topological order in CombineTo

2022-05-07 16:24:31 +00:00

RISCV

[riscv] Add a few more vsetvli insertion tests

2022-05-09 09:08:19 -07:00

SPARC

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SPIRV

[SPIRV] Add SPIR-V specific intrinsics, two passes and tests

2022-05-06 03:02:00 +03:00

SystemZ

[SelectionDAG] Constant fold (sext_inreg undef, VT) to 0 instead of undef.

2022-05-05 09:45:35 -07:00

Thumb

[ARM] Only update the successor edges for immediate predecessors of PrologueMBB

2022-05-03 12:36:35 +01:00

Thumb2

[DAG][PowerPC] Combine shuffle(bitcast(X), Mask) to bitcast(shuffle(X, Mask'))

2022-05-06 10:50:31 +01:00

VE

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WebAssembly

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WinCFGuard

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WinEH

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X86

[X86] insertps-combine.ll - show address math in checks

2022-05-09 16:01:42 +01:00

XCore

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