f7bd5ebd3b
. swap 4-bit register encoding, 16-bit offset and 32-bit imm to support big endian archs . add a test Reported-by: David S. Miller <davem@davemloft.net> Signed-off-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 301653
19 lines
746 B
LLVM
19 lines
746 B
LLVM
; RUN: llc -march=bpfeb -show-mc-encoding < %s | FileCheck %s
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; Function Attrs: nounwind
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define i32 @bpf_prog1(i8* nocapture readnone) local_unnamed_addr #0 {
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; CHECK: r1 = 590618314553ll # encoding: [0x18,0x10,0x00,0x00,0x83,0x98,0x47,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x89]
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; CHECK: r1 += -1879113726 # encoding: [0x07,0x10,0x00,0x00,0x8f,0xff,0x00,0x02]
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; CHECK: r0 = *(u64 *)(r1 + 0) # encoding: [0x79,0x01,0x00,0x00,0x00,0x00,0x00,0x00]
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%2 = alloca i64, align 8
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%3 = bitcast i64* %2 to i8*
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store volatile i64 590618314553, i64* %2, align 8
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%4 = load volatile i64, i64* %2, align 8
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%5 = add i64 %4, -1879113726
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%6 = inttoptr i64 %5 to i64*
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%7 = load i64, i64* %6, align 8
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%8 = trunc i64 %7 to i32
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ret i32 %8
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}
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