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clang-p2996/llvm/test/CodeGen/AMDGPU
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Nicolai Haehnle 7a9c03f484 AMDGPU: Select MIMG instructions manually in SITargetLowering 
Summary:
Having TableGen patterns for image intrinsics is hitting limitations:
for D16 we already have to manually pre-lower the packing of data
values, and we will have to do the same for A16 eventually.

Since there is already some custom C++ code anyway, it is arguably easier
to just do everything in C++, now that we can use the beefed-up generic
tables backend of TableGen to provide all the required metadata and map
intrinsics to corresponding opcodes. With this approach, all image
intrinsic lowering happens in SITargetLowering::lowerImage. That code is
dense due to all the cases that it handles, but it should still be easier
to follow than what we had before, by virtue of it all being done in a
single location, and by virtue of not relying on the TableGen pattern
magic that very few people really understand.

This means that we will have MachineSDNodes with MIMG instructions
during DAG combining, but that seems alright: previously we had
intrinsic nodes instead, but those are similarly opaque to the generic
CodeGen infrastructure, and the final pattern matching just did a 1:1
translation to machine instructions anyway. If anything, the fact that
we now merge the address words into a vector before DAG combine should
be an advantage.

Change-Id: I417f26bd88f54ce9781c1668acc01f3f99774de6

Reviewers: arsenm, rampitec, rtaylor, tstellar

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D48017

llvm-svn: 335228
2018-06-21 13:36:57 +00:00
..
GlobalISel
AMDGPU/GlobalISel: Implement select() for @llvm.amdgcn.cvt.pkrtz
2018-06-14 19:26:37 +00:00
32-bit-local-address-space.ll
…
add_i64.ll
…
add_i128.ll
…
add-debug.ll
…
add.i16.ll
Allow target to decide when to cluster loads/stores in misched
2017-09-13 22:20:47 +00:00
add.ll
AMDGPU: Fix broken check lines
2018-05-29 19:35:53 +00:00
add.v2i16.ll
AMDGPU: Make v2i16/v2f16 legal on VI
2018-05-22 06:32:10 +00:00
addrspacecast-captured.ll
…
addrspacecast-constantexpr.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
addrspacecast.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
adjust-writemask-invalid-copy.ll
AMDGPU: image_getlod and image_getresinfo do not read memory
2017-12-08 20:00:57 +00:00
alignbit-pat.ll
…
alloca.ll
LLParser: add an argument for overriding data layout and do not check alloca addr space
2018-01-30 22:32:39 +00:00
always-uniform.ll
…
amdgcn.bitcast.ll
AMDGPU: Make v4i16/v4f16 legal
2018-06-15 15:15:46 +00:00
amdgcn.private-memory.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
amdgpu-alias-analysis.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
amdgpu-codegenprepare-fdiv.ll
…
amdgpu-codegenprepare-i16-to-i32.ll
…
amdgpu-inline.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
amdgpu-shader-calling-convention.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
amdgpu.private-memory.ll
AMDGPU: Use more custom insert/extract_vector_elt lowering
2018-06-05 19:52:46 +00:00
amdgpu.work-item-intrinsics.deprecated.ll
…
amdhsa-trap-num-sgprs.ll
AMDGPU : Recalculate SGPRs when trap handler is supported
2018-05-16 20:47:48 +00:00
amdpal_scratch_mergedshader.ll
[AMDGPU] Scratch setup fix on AMDPAL gfx9+ merge shader
2018-02-26 14:46:43 +00:00
amdpal-cs.ll
AMDGPU/NFC: Minor clean ups in PAL metadata
2017-10-11 22:41:09 +00:00
amdpal-es.ll
AMDGPU/NFC: Minor clean ups in PAL metadata
2017-10-11 22:41:09 +00:00
amdpal-gs.ll
AMDGPU/NFC: Minor clean ups in PAL metadata
2017-10-11 22:41:09 +00:00
amdpal-hs.ll
AMDGPU/NFC: Minor clean ups in PAL metadata
2017-10-11 22:41:09 +00:00
amdpal-ls.ll
AMDGPU/NFC: Minor clean ups in PAL metadata
2017-10-11 22:41:09 +00:00
amdpal-ps.ll
AMDGPU/NFC: Minor clean ups in PAL metadata
2017-10-11 22:41:09 +00:00
amdpal-psenable.ll
[AMDGPU] For amdpal, widen interpolation mode workaround
2017-10-12 16:16:41 +00:00
amdpal-vs.ll
AMDGPU/NFC: Minor clean ups in PAL metadata
2017-10-11 22:41:09 +00:00
amdpal.ll
[AMDGPU] For OS type AMDPAL, fixed scratch on compute shader
2018-04-10 11:25:15 +00:00
and-gcn.ll
…
and.ll
AMDGPU: Try a lot harder to emit scalar loads
2018-06-07 09:54:49 +00:00
annotate-kernel-features-hsa-call.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
annotate-kernel-features-hsa.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
annotate-kernel-features.ll
…
anonymous-gv.ll
…
any_extend_vector_inreg.ll
…
anyext.ll
AMDGPU: Set v2i32 any_extend to expand
2017-10-05 17:38:30 +00:00
array-ptr-calc-i32.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
array-ptr-calc-i64.ll
AMDGPU: Implement computeKnownBitsForTargetNode for mbcnt
2017-11-13 22:55:05 +00:00
ashr.v2i16.ll
AMDGPU: Try a lot harder to emit scalar loads
2018-06-07 09:54:49 +00:00
atomic_cmp_swap_local.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
atomic_load_add.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
atomic_load_sub.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
attr-amdgpu-flat-work-group-size.ll
AMDGPU: Rename MaxFlatWorkgroupSize to MaxFlatWorkGroupSize for consistency
2017-10-18 17:31:09 +00:00
attr-amdgpu-num-sgpr.ll
…
attr-amdgpu-num-vgpr.ll
…
attr-amdgpu-waves-per-eu.ll
AMDGPU: Fix amdgpu-flat-work-group-size/amdgpu-waves-per-eu check
2017-07-16 19:38:47 +00:00
attr-unparseable.ll
…
barrier-elimination.ll
…
basic-branch.ll
AMDGPU: Try a lot harder to emit scalar loads
2018-06-07 09:54:49 +00:00
basic-call-return.ll
AMDGPU: Fix register name format in tests
2018-03-27 18:39:42 +00:00
basic-loop.ll
AMDGPU: Remove -mcpu=SI
2017-08-07 18:30:35 +00:00
bfe_uint.ll
…
bfe-combine.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
bfe-patterns.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
bfi_int.ll
AMDGPU: Select BFI patterns with 64-bit ints
2018-02-07 00:21:34 +00:00
bfm.ll
…
big_alu.ll
…
bitcast-vector-extract.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
bitreverse-inline-immediates.ll
…
bitreverse.ll
DAG: Fix not truncating when promoting bswap/bitreverse
2018-01-31 23:54:16 +00:00
br_cc.f16.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
branch-condition-and.ll
[AMDGPU] Eliminate no effect instructions before s_endpgm
2017-08-16 04:43:49 +00:00
branch-relax-bundle.ll
AMDGPU: Fix not accounting for instruction size in bundles
2017-10-04 22:59:12 +00:00
branch-relax-spill.ll
…
branch-relaxation.ll
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.
2018-06-20 22:01:04 +00:00
branch-uniformity.ll
…
break-smem-soft-clauses.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
break-vmem-soft-clauses.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
bswap.ll
DAG: Fix not truncating when promoting bswap/bitreverse
2018-01-31 23:54:16 +00:00
buffer-schedule.ll
[AMDGPU] stop buffer_store being moved illegally
2018-02-20 10:03:38 +00:00
bug-vopc-commute.ll
…
build_vector.ll
…
byval-frame-setup.ll
AMDGPU: Increase default stack alignment
2018-03-29 20:22:04 +00:00
call_fs.ll
…
call-argument-types.ll
AMDGPU: Increase default stack alignment
2018-03-29 20:22:04 +00:00
call-encoding.ll
AMDGPU: Remove error on calls for amdgcn
2017-08-03 23:24:05 +00:00
call-graph-register-usage.ll
AMDGPU: Increase default stack alignment
2018-03-29 20:22:04 +00:00
call-preserved-registers.ll
AMDGPU: Fix FP restore from being reordered with stack ops
2018-03-27 18:38:51 +00:00
call-return-types.ll
AMDGPU: Fix not including v2f64 in SReg_128
2018-06-07 12:16:31 +00:00
callee-frame-setup.ll
AMDGPU: Increase default stack alignment
2018-03-29 20:22:04 +00:00
callee-special-input-sgprs.ll
AMDGPU: Increase default stack alignment
2018-03-29 20:22:04 +00:00
callee-special-input-vgprs.ll
AMDGPU: Increase default stack alignment
2018-03-29 20:22:04 +00:00
calling-conventions.ll
[AMDGPU] calling conventions for AMDPAL OS type
2017-09-29 09:51:22 +00:00
captured-frame-index.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
cayman-loop-bug.ll
…
cf_end.ll
…
cf-loop-on-constant.ll
AMDGPU: Try a lot harder to emit scalar loads
2018-06-07 09:54:49 +00:00
cf-stack-bug.ll
…
cgp-addressing-modes-flat.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
cgp-addressing-modes.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
cgp-bitfield-extract.ll
…
clamp-modifier.ll
[AMDGPU] Enabled v2.16 literals for VOP3P
2018-04-17 23:09:05 +00:00
clamp-omod-special-case.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
clamp.ll
AMDGPU: Replace i64 add/sub lowering
2017-11-15 21:51:43 +00:00
cluster-flat-loads-postra.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
cluster-flat-loads.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
cndmask-no-def-vcc.ll
[DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a canonical manner.
2018-02-23 11:50:42 +00:00
coalescer_distribute.ll
…
coalescer_remat.ll
…
coalescer-subrange-crash.ll
…
coalescer-subreg-join.mir
AMDGPU: Turn D16 for MIMG instructions into a regular operand
2018-06-21 13:36:01 +00:00
code-object-v3.ll
AMDHSA/NFC: Code object v3 updates (additional):
2018-06-12 18:33:51 +00:00
codegen-prepare-addrmode-sext.ll
…
collapse-endcf.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
combine_vloads.ll
[AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz environment
2017-11-10 02:03:28 +00:00
combine-and-sext-bool.ll
…
combine-cond-add-sub.ll
[AMDGPU] A trivial fix for a buildbot failure caused by "commit 224a839fcbbead221f872cd32a1dd0c308d37299".
2018-05-02 18:16:39 +00:00
combine-ftrunc.ll
Eliminate ftrunc if source is know to be rounded
2017-10-02 16:57:07 +00:00
comdat.ll
[AMDGPU] Fix compilation failure when IR contains comdat
2018-05-11 20:40:14 +00:00
commute_modifiers.ll
…
commute-compares.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
commute-shifts.ll
…
complex-folding.ll
…
concat_vectors.ll
DAG: Fix creating concat_vectors with illegal type
2018-06-15 12:09:15 +00:00
constant-address-space-32bit.ll
Reapply "AMDGPU: Add 32-bit constant address space"
2018-02-09 16:57:57 +00:00
constant-fold-imm-immreg.mir
AMDGPU: Fix crash when constant folding with physreg operand
2018-03-10 16:05:35 +00:00
constant-fold-mi-operands.ll
…
control-flow-fastregalloc.ll
[AMDGPU] Revert b0efc4fd6 (https://reviews.llvm.org/D40556)
2018-04-25 12:32:46 +00:00
control-flow-optnone.ll
Revert "StructurizeCFG: Test for branch divergence correctly"
2018-02-24 17:29:09 +00:00
convergent-inlineasm.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
copy-illegal-type.ll
…
copy-to-reg.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
ctlz_zero_undef.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
ctlz.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
ctpop16.ll
AMDGPU/GCN: Promote i16 ctpop
2018-03-02 02:50:22 +00:00
ctpop64.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
ctpop.ll
AMDGPU: Replace i64 add/sub lowering
2017-11-15 21:51:43 +00:00
cttz_zero_undef.ll
[DAGCombiner][AMDGPU][X86] Turn cttz/ctlz into cttz_zero_undef/ctlz_zero_undef if we can prove the input is never zero
2018-02-06 23:54:37 +00:00
cube.ll
…
cvt_f32_ubyte.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
cvt_flr_i32_f32.ll
…
cvt_rpi_i32_f32.ll
…
dagcomb-shuffle-vecextend-non2.ll
[DAGCombine] Fix for shuffle to vector extend for non power 2 vectors
2017-10-10 12:45:45 +00:00
dagcombine-reassociate-bug.ll
…
dagcombine-select.ll
Allow binop C1, (select cc, CF, CT) -> select folding
2018-06-20 20:24:20 +00:00
dagcombine-setcc-select.ll
[AMDGPU] setcc (select cc, CT, CF), CF, eq | ne -> xor cc, -1 | cc
2018-06-16 03:46:59 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll
…
dead_copy.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
debug-value2.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
debug-value.ll
[AMDGPU] fix test to survive more FP undef constant folding
2018-03-08 21:30:56 +00:00
debug.ll
…
debugger-emit-prologue.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
debugger-insert-nops.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
debugger-reserve-regs.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
default-fp-mode.ll
…
detect-dead-lanes.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
disconnected-predset-break-bug.ll
…
diverge-extra-formal-args.ll
[AMDGPU] Fix issues for backend divergence tracking
2018-04-18 13:53:31 +00:00
diverge-interp-mov-lower.ll
[AMDGPU] Fix issues for backend divergence tracking
2018-04-18 13:53:31 +00:00
drop-mem-operand-move-smrd.ll
…
ds_read2_offset_order.ll
…
ds_read2_superreg.ll
…
ds_read2.ll
AMDGPU: Track physreg uses in SILoadStoreOptimizer
2018-02-23 10:45:56 +00:00
ds_read2st64.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
ds_write2.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
ds_write2st64.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
ds-combine-large-stride.ll
[AMDGPU] SI Load Store Optimizer: When merging with offset, use V_ADD_{I|U}32_e64
2018-01-22 21:46:43 +00:00
ds-negative-offset-addressing-mode-loop.ll
…
ds-sub-offset.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
dynamic_stackalloc.ll
Fix pointer EVT in SelectionDAGBuilder::visitAlloca
2017-11-16 12:22:19 +00:00
early-if-convert-cost.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
early-if-convert.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
early-inline-alias.ll
…
early-inline.ll
[PassManager] Run global optimizations after the inliner.
2017-10-05 18:06:37 +00:00
elf-header-flags-mach.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
elf-header-flags-xnack.ll
AMDGPU: Bring elf flags in sync with the spec
2018-02-16 22:33:59 +00:00
elf-header-osabi.ll
AMDGPU: Bring elf flags in sync with the spec
2018-02-16 22:33:59 +00:00
elf-notes.ll
AMDHSA: Code object v3 updates
2018-06-12 18:02:46 +00:00
elf.ll
AMDGPU: Correctly set EI_OSABI based on the os
2017-10-04 22:44:13 +00:00
elf.r600.ll
AMDGPU: Correctly set EI_OSABI based on the os
2017-10-04 22:44:13 +00:00
else.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
empty-function.ll
AMDGPU: Remove -mcpu=SI
2017-08-07 18:30:35 +00:00
enable-no-signed-zeros-fp-math.ll
…
endcf-loop-header.ll
…
endpgm-dce.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
enqueue-kernel.ll
[AMDGPU] Change enqueue kernel handle type
2018-06-13 17:31:51 +00:00
env-amdgiz.ll
…
env-amdgizcl.ll
…
exceed-max-sgprs.ll
…
extend-bit-ops-i16.ll
…
extload-align.ll
AMDGPU: Custom lower v4i16/v4f16 vector operations
2018-05-16 11:47:30 +00:00
extload-private.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
extload.ll
…
extract_vector_elt-f16.ll
AMDGPU: Add combine for short vector extract_vector_elts
2018-06-15 15:31:36 +00:00
extract_vector_elt-f64.ll
CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT/SplitVecRes_INSERT_VECTOR_ELT
2017-12-02 22:13:22 +00:00
extract_vector_elt-i8.ll
AMDGPU: Add combine for short vector extract_vector_elts
2018-06-15 15:31:36 +00:00
extract_vector_elt-i16.ll
AMDGPU: Add combine for short vector extract_vector_elts
2018-06-15 15:31:36 +00:00
extract_vector_elt-i64.ll
CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT/SplitVecRes_INSERT_VECTOR_ELT
2017-12-02 22:13:22 +00:00
extract-lowbits.ll
[AMDGPU] Recognize x & ~(-1 << y) pattern.
2018-06-15 09:56:45 +00:00
extract-vector-elt-build-vector-combine.ll
…
extractelt-to-trunc.ll
…
fabs.f16.ll
AMDGPU: Make v4i16/v4f16 legal
2018-06-15 15:15:46 +00:00
fabs.f64.ll
…
fabs.ll
AMDGPU: Use scalar operations for f16 fabs/fneg patterns
2018-06-07 10:15:20 +00:00
fadd64.ll
…
fadd-fma-fmul-combine.ll
…
fadd.f16.ll
Allow target to decide when to cluster loads/stores in misched
2017-09-13 22:20:47 +00:00
fadd.ll
Utilize new SDNode flag functionality to expand current support for fadd
2018-06-18 23:44:59 +00:00
fcanonicalize-elimination.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
fcanonicalize.f16.ll
AMDGPU: Make v2i16/v2f16 legal on VI
2018-05-22 06:32:10 +00:00
fcanonicalize.ll
DAG: Fix not legalizing vector fcanonicalizes
2018-04-26 19:21:37 +00:00
fceil64.ll
…
fceil.ll
…
fcmp64.ll
…
fcmp-cnd.ll
…
fcmp-cnde-int-args.ll
…
fcmp.f16.ll
…
fcmp.ll
…
fconst64.ll
…
fcopysign.f16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
fcopysign.f32.ll
…
fcopysign.f64.ll
[AMDGPU] Prevent post-RA scheduler from breaking memory clauses
2017-09-19 20:54:38 +00:00
fdiv32-to-rcp-folding.ll
[AMDGPU] Improve reciprocal handling
2018-06-06 22:22:32 +00:00
fdiv.f16.ll
Utilize new SDNode flag functionality to expand current support for fdiv
2018-06-15 20:44:55 +00:00
fdiv.f64.ll
…
fdiv.ll
…
fence-amdgiz.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fence-barrier.ll
[AMDGPU][Waitcnt] Remove obsolete waitcnt option
2018-05-25 20:24:08 +00:00
fetch-limits.r600.ll
…
fetch-limits.r700+.ll
…
ffloor.f64.ll
…
ffloor.ll
…
fix-vgpr-copies.mir
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
fix-wwm-liveness.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
flat_atomics_i64.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
flat_atomics.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
flat-address-space.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
flat-for-global-subtarget-feature.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
flat-load-clustering.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
flat-scratch-reg.ll
…
floor.ll
…
fma-combine.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
fma.f64.ll
…
fma.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
fmad.ll
…
fmax3.f64.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
fmax3.ll
AMDGPU: Make v2i16/v2f16 legal on VI
2018-05-22 06:32:10 +00:00
fmax_legacy.f64.ll
…
fmax_legacy.ll
…
fmax.ll
…
fmaxnum.f64.ll
…
fmaxnum.ll
…
fmed3.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
fmin3.ll
AMDGPU: Make v2i16/v2f16 legal on VI
2018-05-22 06:32:10 +00:00
fmin_fmax_legacy.amdgcn.ll
…
fmin_legacy.f64.ll
…
fmin_legacy.ll
…
fmin.ll
…
fminnum.f64.ll
AMDGPU: Remove -mcpu=SI
2017-08-07 18:30:35 +00:00
fminnum.ll
…
fmul64.ll
…
fmul-2-combine-multi-use.ll
…
fmul.f16.ll
AMDGPU: Fix missing test coverage for some 16-bit and packed ops
2018-05-22 20:42:00 +00:00
fmul.ll
…
fmuladd.f16.ll
[AMDGPU] Removed redundant run lines for fmuladd.f16 test. NFC.
2018-02-20 19:19:56 +00:00
fmuladd.f32.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
fmuladd.f64.ll
…
fmuladd.v2f16.ll
[AMDGPU] Enabled v2.16 literals for VOP3P
2018-04-17 23:09:05 +00:00
fnearbyint.ll
…
fneg-combines.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
fneg-fabs.f16.ll
AMDGPU: Use scalar operations for f16 fabs/fneg patterns
2018-06-07 10:15:20 +00:00
fneg-fabs.f64.ll
…
fneg-fabs.ll
…
fneg.f16.ll
AMDGPU: Use scalar operations for f16 fabs/fneg patterns
2018-06-07 10:15:20 +00:00
fneg.f64.ll
…
fneg.ll
AMDGPU: Implement hasBitPreservingFPLogic
2017-10-13 21:10:22 +00:00
fold-cndmask.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fold-fmul-to-neg-abs.ll
…
fold-imm-f16-f32.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fold-immediate-output-mods.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fold-implicit-operand.mir
AMDGPU: Don't crash when trying to fold implicit operands
2018-02-08 01:12:46 +00:00
fold-multiple.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fold-operands-order.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fp16_to_fp32.ll
…
fp16_to_fp64.ll
…
fp32_to_fp16.ll
…
fp_to_sint.f64.ll
…
fp_to_sint.ll
…
fp_to_uint.f64.ll
…
fp_to_uint.ll
…
fp-classify.ll
…
fpext-free.ll
AMDGPU: Look for src mods before fp_extend
2017-10-13 20:45:49 +00:00
fpext.f16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
fpext.ll
…
fptosi.f16.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
fptoui.f16.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
fptrunc.f16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
fptrunc.ll
…
fract.f64.ll
…
fract.ll
…
frame-index-amdgiz.ll
[AMDGPU] Prevent post-RA scheduler from breaking memory clauses
2017-09-19 20:54:38 +00:00
frame-index-elimination.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
frem.ll
…
fsqrt.f64.ll
…
fsqrt.ll
…
fsub64.ll
…
fsub.f16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
fsub.ll
…
ftrunc.f64.ll
AMDGPU: Remove -mcpu=SI
2017-08-07 18:30:35 +00:00
ftrunc.ll
…
function-args.ll
AMDGPU: Make v4i16/v4f16 legal
2018-06-15 15:15:46 +00:00
function-returns.ll
AMDGPU: Make v4i16/v4f16 legal
2018-06-15 15:15:46 +00:00
gep-address-space.ll
…
global_atomics_i64.ll
AMDGPU: Start selecting global instructions
2017-07-29 01:03:53 +00:00
global_atomics.ll
AMDGPU: Start selecting global instructions
2017-07-29 01:03:53 +00:00
global_smrd_cfg.ll
…
global_smrd.ll
…
global-constant.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
global-directive.ll
…
global-extload-i16.ll
…
global-smrd-unknown.ll
AMDGPU: Don't use undef in a test
2018-05-08 18:43:34 +00:00
global-variable-relocs.ll
…
gv-const-addrspace.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
gv-offset-folding.ll
…
half.ll
AMDGPU: Make v4i16/v4f16 legal
2018-06-15 15:15:46 +00:00
hazard-inlineasm.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
hazard.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
hoist-cond.ll
…
hsa-default-device.ll
…
hsa-fp-mode.ll
…
hsa-func-align.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
hsa-func.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
hsa-globals.ll
…
hsa-group-segment.ll
…
hsa-metadata-deduce-ro-arg.ll
AMDGPU: Report Arg's Value name in metadata if kernel_arg_name metadata is not available
2017-12-08 19:22:12 +00:00
hsa-metadata-enqueu-kernel.ll
AMDGPU/Metadata: Always report a fixed number of hidden arguments
2018-04-05 20:46:04 +00:00
hsa-metadata-from-llvm-ir-full.ll
AMDGPU: Bring processors and features in sync with the spec
2018-02-16 21:26:25 +00:00
hsa-metadata-hidden-args.ll
AMDGPU/Metadata: Always report a fixed number of hidden arguments
2018-04-05 20:46:04 +00:00
hsa-metadata-images.ll
AMDGPU: Bring processors and features in sync with the spec
2018-02-16 21:26:25 +00:00
hsa-metadata-invalid-ocl-version-1.ll
llvm-readobj: Print AMDGPU note contents
2017-10-14 18:21:42 +00:00
hsa-metadata-invalid-ocl-version-2.ll
llvm-readobj: Print AMDGPU note contents
2017-10-14 18:21:42 +00:00
hsa-metadata-invalid-ocl-version-3.ll
llvm-readobj: Print AMDGPU note contents
2017-10-14 18:21:42 +00:00
hsa-metadata-kernel-code-props.ll
[AMDGPU] Add perf hints to functions
2018-05-25 17:25:12 +00:00
hsa-metadata-kernel-debug-props.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
hsa-note-no-func.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
hsa.ll
AMDGPU: Detect kernarg segment pointer
2017-07-14 00:11:13 +00:00
huge-private-buffer.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
i1-copy-from-loop.ll
AMDGPU: Fix copying i1 value out of loop with non-uniform exit
2018-04-04 10:57:58 +00:00
i1-copy-implicit-def.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
i1-copy-phi.ll
[AMDGPU] Optimize SI_IF lowering for simple if regions
2017-07-26 21:29:15 +00:00
i8-to-double-to-float.ll
…
icmp64.ll
…
icmp-select-sete-reverse-args.ll
…
icmp.i16.ll
…
illegal-sgpr-to-vgpr-copy.ll
…
image-attributes.ll
…
image-resource-id.ll
…
image-schedule.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
imm16.ll
AMDGPU: Try a lot harder to emit scalar loads
2018-06-07 09:54:49 +00:00
imm.ll
[InstSimplify] fp_binop X, NaN --> NaN
2018-03-21 19:31:53 +00:00
immv216.ll
AMDGPU: Make v2i16/v2f16 legal on VI
2018-05-22 06:32:10 +00:00
indirect-addressing-si-noopt.ll
AMDGPU Tests: Change a case to be run with -O0
2017-12-06 17:40:09 +00:00
indirect-addressing-si.ll
AMDGPU/SI: Turn off GPR Indexing Mode immediately after the interested instruction.
2018-02-16 16:31:30 +00:00
indirect-private-64.ll
AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements
2018-02-16 19:14:17 +00:00
infer-addrpace-pipeline.ll
…
infinite-loop-evergreen.ll
…
infinite-loop.ll
AMDGPU/SI: Handle infinite loop for the structurizer to work with CFG with infinite loops.
2018-05-17 16:45:01 +00:00
inline-asm.ll
AMDGPU: Fix assert on n inline asm constraint
2017-08-09 20:09:35 +00:00
inline-attr.ll
[AMDGPU] Set fast-math flags on functions given the options
2017-09-29 23:40:19 +00:00
inline-calls.ll
AMDGPU: Remove -mcpu=SI
2017-08-07 18:30:35 +00:00
inline-constraints.ll
[AMDGPU] Inline asm - added i16, half and i128 types support
2018-06-08 16:29:04 +00:00
inlineasm-16.ll
[AMDGPU] Inline asm - added i16, half and i128 types support
2018-06-08 16:29:04 +00:00
inlineasm-illegal-type.ll
[AMDGPU] Inline asm - added i16, half and i128 types support
2018-06-08 16:29:04 +00:00
inlineasm-packed.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
InlineAsmCrash.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
input-mods.ll
…
insert_subreg.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
insert_vector_elt.ll
AMDGPU: Try a lot harder to emit scalar loads
2018-06-07 09:54:49 +00:00
insert_vector_elt.v2i16.ll
AMDGPU: Make v2i16/v2f16 legal on VI
2018-05-22 06:32:10 +00:00
insert-skips-kill-uncond.mir
AMDGPU: Add implicit def of SCC to kill and indirect pseudos
2018-06-21 13:36:08 +00:00
insert-waitcnts-callee.mir
[AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained.
2018-04-27 17:59:15 +00:00
insert-waitcnts-exp.mir
[AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained.
2018-04-27 17:59:15 +00:00
inserted-wait-states.mir
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
internalize.ll
[AMDGPU] Port of HSAIL inliner
2017-09-20 04:25:58 +00:00
invalid-addrspacecast.ll
…
invalid-alloca.ll
LLParser: add an argument for overriding data layout and do not check alloca addr space
2018-01-30 22:32:39 +00:00
invariant-load-no-alias-store.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
invert-br-undef-vcc.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
ipra.ll
AMDGPU: Enable IPRA
2017-11-28 23:40:12 +00:00
jump-address.ll
[AMDGPU] change test to avoid NaN math
2018-03-19 19:26:22 +00:00
kcache-fold.ll
…
kernarg-stack-alignment.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
kernel-args.ll
AMDGPU: Make v4i16/v4f16 legal
2018-06-15 15:15:46 +00:00
knownbits-recursion.ll
[AMDGPU] Testcase for computeKnownBits recursion. NFC.
2017-09-01 22:25:22 +00:00
large-alloca-compute.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
large-alloca-graphics.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
large-constant-initializer.ll
AMDGPU: Remove -mcpu=SI
2017-08-07 18:30:35 +00:00
large-work-group-promote-alloca.ll
AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements
2018-02-16 19:14:17 +00:00
lds_atomic_f32.ll
[AMDGPU] fix LDS f32 intrinsics
2018-01-26 11:09:38 +00:00
lds-alignment.ll
[NFC] fix trivial typos in comments and documents
2018-01-29 05:17:03 +00:00
lds-global-non-entry-func.ll
AMDGPU: Error on LDS global address in functions
2018-06-08 08:05:54 +00:00
lds-initializer.ll
AMDGPU: Remove -mcpu=SI
2017-08-07 18:30:35 +00:00
lds-m0-init-in-loop.ll
…
lds-oqap-crash.ll
…
lds-output-queue.ll
[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output
2017-11-30 12:12:19 +00:00
lds-size.ll
…
lds-zero-initializer.ll
AMDGPU: Remove -mcpu=SI
2017-08-07 18:30:35 +00:00
legalize-fp-load-invariant.ll
DAG: Stop dropping invariant/dereferencable
2018-06-05 14:52:24 +00:00
legalizedag-bug-expand-setcc.ll
…
limit-coalesce.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
lit.local.cfg
…
literals.ll
…
liveness.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
llvm.amdgcn.alignb.ll
…
llvm.amdgcn.atomic.dec.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
llvm.amdgcn.atomic.inc.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
llvm.amdgcn.buffer.atomic.ll
AMDGPU: Lower buffer store and atomic intrinsics manually
2017-11-09 01:52:48 +00:00
llvm.amdgcn.buffer.load.format.d16.ll
AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the target has UnpackedD16VMem feature.
2018-02-01 18:41:33 +00:00
llvm.amdgcn.buffer.load.format.ll
AMDGPU: Split MUBUF offset into aligned components
2017-10-10 12:22:23 +00:00
llvm.amdgcn.buffer.load.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.buffer.store.format.d16.ll
AMDGPU: Make v4i16/v4f16 legal
2018-06-15 15:15:46 +00:00
llvm.amdgcn.buffer.store.format.ll
[AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account.
2018-04-26 16:11:19 +00:00
llvm.amdgcn.buffer.store.ll
[AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account.
2018-04-26 16:11:19 +00:00
llvm.amdgcn.buffer.wbinvl1.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.buffer.wbinvl1.sc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.buffer.wbinvl1.vol.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.class.f16.ll
AMDGPU: Try a lot harder to emit scalar loads
2018-06-07 09:54:49 +00:00
llvm.amdgcn.class.ll
…
llvm.amdgcn.cos.f16.ll
…
llvm.amdgcn.cos.ll
…
llvm.amdgcn.cubeid.ll
…
llvm.amdgcn.cubema.ll
…
llvm.amdgcn.cubesc.ll
…
llvm.amdgcn.cubetc.ll
…
llvm.amdgcn.cvt.pk.i16.ll
AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
2018-01-31 20:18:04 +00:00
llvm.amdgcn.cvt.pk.u16.ll
AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
2018-01-31 20:18:04 +00:00
llvm.amdgcn.cvt.pknorm.i16.ll
AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
2018-01-31 20:18:04 +00:00
llvm.amdgcn.cvt.pknorm.u16.ll
AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
2018-01-31 20:18:04 +00:00
llvm.amdgcn.cvt.pkrtz.ll
AMDGPU: Make undef legal for v2i16/v2f16
2018-05-13 10:04:38 +00:00
llvm.amdgcn.dispatch.id.ll
…
llvm.amdgcn.dispatch.ptr.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.amdgcn.div.fixup.f16.ll
AMDGPU: Fix breaking SMEM clauses
2017-11-17 04:18:24 +00:00
llvm.amdgcn.div.fixup.ll
…
llvm.amdgcn.div.fmas.ll
[AMDGPU] Optimize SI_IF lowering for simple if regions
2017-07-26 21:29:15 +00:00
llvm.amdgcn.div.scale.ll
AMDGPU: Fix handling of div_scale with undef inputs
2017-08-01 20:49:41 +00:00
llvm.amdgcn.ds.bpermute.ll
[DAGCombine] (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2)
2017-09-14 10:38:30 +00:00
llvm.amdgcn.ds.permute.ll
…
llvm.amdgcn.ds.swizzle.ll
…
llvm.amdgcn.exp.compr.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
llvm.amdgcn.exp.ll
…
llvm.amdgcn.fcmp.ll
…
llvm.amdgcn.fdiv.fast.ll
…
llvm.amdgcn.fdot2.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
llvm.amdgcn.fmed3.f16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
llvm.amdgcn.fmed3.ll
…
llvm.amdgcn.fmul.legacy.ll
…
llvm.amdgcn.fract.f16.ll
…
llvm.amdgcn.fract.ll
…
llvm.amdgcn.frexp.exp.f16.ll
…
llvm.amdgcn.frexp.exp.ll
…
llvm.amdgcn.frexp.mant.f16.ll
…
llvm.amdgcn.frexp.mant.ll
…
llvm.amdgcn.groupstaticsize.ll
…
llvm.amdgcn.icmp.ll
…
llvm.amdgcn.image.atomic.dim.ll
AMDGPU: Dimension-aware image intrinsics
2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.atomic.ll
AMDGPU: Lower buffer store and atomic intrinsics manually
2017-11-09 01:52:48 +00:00
llvm.amdgcn.image.d16.dim.ll
AMDGPU: Dimension-aware image intrinsics
2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.d16.ll
AMDGPU: Make v4i16/v4f16 legal
2018-06-15 15:15:46 +00:00
llvm.amdgcn.image.dim.ll
AMDGPU: Make v2i16/v2f16 legal on VI
2018-05-22 06:32:10 +00:00
llvm.amdgcn.image.gather4.d16.dim.ll
AMDGPU: Dimension-aware image intrinsics
2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.gather4.d16.ll
AMDGPU: Add combine for trunc of bitcast from build_vector
2018-05-09 18:37:39 +00:00
llvm.amdgcn.image.gather4.dim.ll
AMDGPU: Dimension-aware image intrinsics
2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.gather4.ll
[AMDGPU][MC] Corrected GATHER4 opcodes
2018-03-12 15:03:34 +00:00
llvm.amdgcn.image.getlod.dim.ll
AMDGPU: Select MIMG instructions manually in SITargetLowering
2018-06-21 13:36:57 +00:00
llvm.amdgcn.image.getlod.ll
AMDGPU: image_getlod and image_getresinfo do not read memory
2017-12-08 20:00:57 +00:00
llvm.amdgcn.image.ll
[AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account.
2018-04-26 16:11:19 +00:00
llvm.amdgcn.image.sample.d16.dim.ll
AMDGPU: Dimension-aware image intrinsics
2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.sample.d16.ll
AMDGPU: Add combine for trunc of bitcast from build_vector
2018-05-09 18:37:39 +00:00
llvm.amdgcn.image.sample.dim.ll
AMDGPU: Dimension-aware image intrinsics
2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.sample.ll
…
llvm.amdgcn.image.sample.o.ll
…
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.amdgcn.implicit.buffer.ptr.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.amdgcn.implicitarg.ptr.ll
[AMDGPU] Update OpenCL to use 48 bytes of implicit arguments for AMDGPU
2018-03-23 18:58:47 +00:00
llvm.amdgcn.init.exec.ll
AMDGPU: Fix a corner case crash in SIOptimizeExecMasking
2018-04-23 13:05:50 +00:00
llvm.amdgcn.interp.ll
[AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP opcodes
2018-03-16 16:38:04 +00:00
llvm.amdgcn.kernarg.segment.ptr.ll
AMDGPU: Round up kernel argument allocation size
2018-05-29 19:35:00 +00:00
llvm.amdgcn.kill.ll
AMDGPU: Add implicit def of SCC to kill and indirect pseudos
2018-06-21 13:36:08 +00:00
llvm.amdgcn.ldexp.f16.ll
…
llvm.amdgcn.ldexp.ll
…
llvm.amdgcn.lerp.ll
…
llvm.amdgcn.log.clamp.ll
…
llvm.amdgcn.mbcnt.ll
AMDGPU: Implement computeKnownBitsForTargetNode for mbcnt
2017-11-13 22:55:05 +00:00
llvm.amdgcn.mov.dpp.ll
[AMDGPU] Add pseudo "old" source to all DPP instructions
2017-08-07 19:10:56 +00:00
llvm.amdgcn.mqsad.pk.u16.u8.ll
…
llvm.amdgcn.mqsad.u32.u8.ll
…
llvm.amdgcn.msad.u8.ll
…
llvm.amdgcn.ps.live.ll
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
2017-09-29 15:37:31 +00:00
llvm.amdgcn.qsad.pk.u16.u8.ll
…
llvm.amdgcn.queue.ptr.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.amdgcn.rcp.f16.ll
…
llvm.amdgcn.rcp.legacy.ll
…
llvm.amdgcn.rcp.ll
…
llvm.amdgcn.readfirstlane.ll
…
llvm.amdgcn.readlane.ll
…
llvm.amdgcn.rsq.clamp.ll
…
llvm.amdgcn.rsq.f16.ll
…
llvm.amdgcn.rsq.legacy.ll
…
llvm.amdgcn.rsq.ll
…
llvm.amdgcn.s.barrier.ll
AMDGPU: Start selecting global instructions
2017-07-29 01:03:53 +00:00
llvm.amdgcn.s.dcache.inv.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.dcache.inv.vol.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.dcache.wb.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.dcache.wb.vol.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.decperflevel.ll
…
llvm.amdgcn.s.getpc.ll
…
llvm.amdgcn.s.getreg.ll
…
llvm.amdgcn.s.incperflevel.ll
…
llvm.amdgcn.s.memrealtime.ll
…
llvm.amdgcn.s.memtime.ll
…
llvm.amdgcn.s.sleep.ll
…
llvm.amdgcn.s.waitcnt.ll
[AMDGPU] Combine adjacent waitcounts in a single strongest wait
2018-02-15 22:03:55 +00:00
llvm.amdgcn.sad.hi.u8.ll
…
llvm.amdgcn.sad.u8.ll
…
llvm.amdgcn.sad.u16.ll
…
llvm.amdgcn.sbfe.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
llvm.amdgcn.sdot2.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
llvm.amdgcn.sdot4.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
llvm.amdgcn.sdot8.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
llvm.amdgcn.sendmsg.ll
AMDGPU: Legalize the operand of SI_INIT_M0
2018-04-20 07:14:25 +00:00
llvm.amdgcn.set.inactive.ll
[AMDGPU] Implement llvm.amdgcn.set.inactive intrinsic
2017-08-04 18:36:54 +00:00
llvm.amdgcn.sffbh.ll
…
llvm.amdgcn.sin.f16.ll
…
llvm.amdgcn.sin.ll
…
llvm.amdgcn.tbuffer.load.d16.ll
AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the target has UnpackedD16VMem feature.
2018-02-01 18:41:33 +00:00
llvm.amdgcn.tbuffer.load.ll
…
llvm.amdgcn.tbuffer.store.d16.ll
AMDGPU: Make v4i16/v4f16 legal
2018-06-15 15:15:46 +00:00
llvm.amdgcn.tbuffer.store.ll
[AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account.
2018-04-26 16:11:19 +00:00
llvm.amdgcn.trig.preop.ll
…
llvm.amdgcn.ubfe.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
llvm.amdgcn.udot2.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
llvm.amdgcn.udot4.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
llvm.amdgcn.udot8.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
llvm.amdgcn.unreachable.ll
…
llvm.amdgcn.update.dpp.ll
[AMDGPU] Add llvm.amdgpu.update.dpp intrinsic
2017-08-08 18:52:22 +00:00
llvm.amdgcn.wave.barrier.ll
…
llvm.amdgcn.workgroup.id.ll
…
llvm.amdgcn.workitem.id.ll
…
llvm.amdgcn.wqm.vote.ll
AMDGPU: Add llvm.amdgcn.wqm.vote intrinsic
2017-10-24 10:26:59 +00:00
llvm.amdgcn.writelane.ll
[AMDGPU] added writelane intrinsic
2018-02-28 19:10:32 +00:00
llvm.AMDGPU.kill.ll
…
llvm.ceil.f16.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
llvm.cos.f16.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
llvm.cos.ll
…
llvm.dbg.value.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
llvm.exp2.f16.ll
[AMDGPU] Fixed some instructions latencies
2018-03-30 16:19:13 +00:00
llvm.exp2.ll
…
llvm.floor.f16.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
llvm.fma.f16.ll
AMDGPU: Make v2i16/v2f16 legal on VI
2018-05-22 06:32:10 +00:00
llvm.fmuladd.f16.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
llvm.log2.f16.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
llvm.log2.ll
AMDGPU: Remove -mcpu=SI
2017-08-07 18:30:35 +00:00
llvm.log10.f16.ll
[AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics
2017-11-27 13:26:38 +00:00
llvm.log10.ll
[AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics
2017-11-27 13:26:38 +00:00
llvm.log.f16.ll
[AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics
2017-11-27 13:26:38 +00:00
llvm.log.ll
[AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics
2017-11-27 13:26:38 +00:00
llvm.maxnum.f16.ll
AMDGPU: Fix missing test coverage for some 16-bit and packed ops
2018-05-22 20:42:00 +00:00
llvm.memcpy.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.minnum.f16.ll
AMDGPU: Fix missing test coverage for some 16-bit and packed ops
2018-05-22 20:42:00 +00:00
llvm.pow.ll
…
llvm.r600.cube.ll
…
llvm.r600.dot4.ll
…
llvm.r600.group.barrier.ll
…
llvm.r600.read.local.size.ll
…
llvm.r600.recipsqrt.clamped.ll
…
llvm.r600.recipsqrt.ieee.ll
…
llvm.r600.tex.ll
…
llvm.rint.f16.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
llvm.rint.f64.ll
AMDGPU: Remove -mcpu=SI
2017-08-07 18:30:35 +00:00
llvm.rint.ll
…
llvm.round.f64.ll
…
llvm.round.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
llvm.SI.load.dword.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.SI.tbuffer.store.ll
…
llvm.sin.f16.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
llvm.sin.ll
…
llvm.sqrt.f16.ll
[AMDGPU] Fixed some instructions latencies
2018-03-30 16:19:13 +00:00
llvm.trunc.f16.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
load-constant-f32.ll
[AMDGPU] Increased vector length for global/constant loads.
2018-03-07 17:09:18 +00:00
load-constant-f64.ll
[AMDGPU] Increased vector length for global/constant loads.
2018-03-07 17:09:18 +00:00
load-constant-i1.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
load-constant-i8.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
load-constant-i16.ll
AMDGPU: Fix selection error on constant loads with < 4 byte alignment
2018-03-29 19:59:28 +00:00
load-constant-i32.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
load-constant-i64.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
load-global-f32.ll
…
load-global-f64.ll
…
load-global-i1.ll
[AMDGPU] Fix pointer info for pseudo source for r600
2017-11-10 01:53:24 +00:00
load-global-i8.ll
Re-land MachineInstr: Reason locally about some memory objects before going to AA.
2017-08-30 14:57:12 +00:00
load-global-i16.ll
AMDGPU: Fix selection error on constant loads with < 4 byte alignment
2018-03-29 19:59:28 +00:00
load-global-i32.ll
[AMDGPU] Prevent post-RA scheduler from breaking memory clauses
2017-09-19 20:54:38 +00:00
load-global-i64.ll
…
load-hi16.ll
AMDGPU: Add D16 instructions preserve unused bits feature
2018-05-04 20:06:57 +00:00
load-input-fold.ll
…
load-lo16.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
load-local-f32-no-ds128.ll
AMDGPU: Add a missing test for the 128-bit local addr space option
2018-05-15 21:41:57 +00:00
load-local-f32.ll
AMDGPU: enable 128-bit for local addr space under an option
2018-04-10 22:48:23 +00:00
load-local-f64.ll
AMDGPU: enable 128-bit for local addr space under an option
2018-04-10 22:48:23 +00:00
load-local-i1.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
load-local-i8.ll
AMDGPU: enable 128-bit for local addr space under an option
2018-04-10 22:48:23 +00:00
load-local-i16.ll
AMDGPU: enable 128-bit for local addr space under an option
2018-04-10 22:48:23 +00:00
load-local-i32.ll
AMDGPU: enable 128-bit for local addr space under an option
2018-04-10 22:48:23 +00:00
load-local-i64.ll
AMDGPU: enable 128-bit for local addr space under an option
2018-04-10 22:48:23 +00:00
load-private-double16-amdgiz.ll
CodeGen: Fix pointer info in expandUnalignedLoad/Store
2017-09-29 23:31:14 +00:00
load-select-ptr.ll
AMDGPU: Fix crash when MachinePointerInfo invalid
2018-03-27 18:39:45 +00:00
load-weird-sizes.ll
[AMDGPU] Prevent post-RA scheduler from breaking memory clauses
2017-09-19 20:54:38 +00:00
local-64.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
local-atomics64.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
local-atomics.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
local-memory.amdgcn.ll
…
local-memory.ll
…
local-memory.r600.ll
…
local-stack-slot-offset.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
loop_break.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
loop_exit_with_xor.ll
[AMDGPU] Fixed incorrect break from loop
2018-05-25 07:55:04 +00:00
loop-address.ll
…
loop-idiom.ll
AMDGPU: Remove -mcpu=SI
2017-08-07 18:30:35 +00:00
lower-mem-intrinsics.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
lower-range-metadata-intrinsic-call.ll
…
lshl64-to-32.ll
[AMDGPU] computeKnownBitsForTargetNode for 24 bit mul
2017-08-28 16:35:37 +00:00
lshr.v2i16.ll
AMDGPU: Try a lot harder to emit scalar loads
2018-06-07 09:54:49 +00:00
macro-fusion-cluster-vcc-uses.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
mad24-get-global-id.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
mad_64_32.ll
[AMDGPU] Fixed some instructions latencies
2018-03-30 16:19:13 +00:00
mad_int24.ll
…
mad_uint24.ll
…
mad-combine.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
mad-mix-hi.ll
[AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*
2017-11-17 15:15:40 +00:00
mad-mix-lo.ll
AMDGPU: Make v4i16/v4f16 legal
2018-06-15 15:15:46 +00:00
mad-mix.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
madak.ll
[AMDGPU] Fixed madak.ll test on VI, added GFX10. NFC.
2018-02-23 23:53:27 +00:00
madmk.ll
[AMDGPU] fix tests to be independent of FP undef
2018-03-10 16:39:59 +00:00
max3.ll
…
max-literals.ll
…
max.i16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
max.ll
…
mem-builtins.ll
AMDGPU: Remove error on calls for amdgcn
2017-08-03 23:24:05 +00:00
memory_clause.ll
[AMDGPU] Construct memory clauses before RA
2018-05-31 20:13:51 +00:00
memory_clause.mir
AMDGPU: Turn D16 for MIMG instructions into a regular operand
2018-06-21 13:36:01 +00:00
memory-legalizer-atomic-cmpxchg.ll
[AMDGPU] Cleanup in memory legalizer tests. NFC.
2018-02-13 20:03:32 +00:00
memory-legalizer-atomic-fence.ll
[AMDGPU] Cleanup in memory legalizer tests. NFC.
2018-02-13 20:03:32 +00:00
memory-legalizer-atomic-insert-end.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
memory-legalizer-atomic-rmw.ll
[AMDGPU] Cleanup in memory legalizer tests. NFC.
2018-02-13 20:03:32 +00:00
memory-legalizer-invalid-addrspace.mir
[AMDGPU] Simplify memory legalizer
2018-06-07 22:28:32 +00:00
memory-legalizer-invalid-syncscope.ll
[AMDGPU] Simplify memory legalizer
2018-06-07 22:28:32 +00:00
memory-legalizer-load.ll
[AMDGPU] Simplify memory legalizer
2018-06-07 22:28:32 +00:00
memory-legalizer-local.mir
[AMDGPU] Simplify memory legalizer
2018-06-07 22:28:32 +00:00
memory-legalizer-multiple-mem-operands-atomics.mir
[AMDGPU] Simplify memory legalizer
2018-06-07 22:28:32 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
memory-legalizer-region.mir
[AMDGPU] Simplify memory legalizer
2018-06-07 22:28:32 +00:00
memory-legalizer-store-infinite-loop.ll
[AMDGPU] Turn off MergeConsecutiveStores() before Instruction Selection for AMDGPU. Commit dbbb6c5fc3642987430866dffdf710df4f616ac7 turned on MergeConsecutiveStores() before Instruction Selection for all targets. Enough AMDGPU compiles go into an infinite loop ( MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges; MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off until the issues can be addressed.
2017-12-19 19:26:23 +00:00
memory-legalizer-store.ll
[AMDGPU] Cleanup in memory legalizer tests. NFC.
2018-02-13 20:03:32 +00:00
merge-load-store-physreg.mir
AMDGPU: Track physreg uses in SILoadStoreOptimizer
2018-02-23 10:45:56 +00:00
merge-load-store-vreg.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
merge-load-store.mir
AMDGPU: Fix incorrect reordering when inline asm defines LDS address
2018-02-08 01:56:14 +00:00
merge-m0.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
merge-store-crash.ll
…
merge-store-usedef.ll
…
merge-stores.ll
AMDGPU: Merge BUFFER_STORE_DWORD_OFFEN/OFFSET into x2, x4
2017-11-09 01:52:55 +00:00
mesa_regression.ll
…
min3.ll
…
min.ll
AMDGPU: Try a lot harder to emit scalar loads
2018-06-07 09:54:49 +00:00
misched-killflags.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
missing-store.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
move-addr64-rsrc-dead-subreg-writes.ll
[AMDGPU] Prevent post-RA scheduler from breaking memory clauses
2017-09-19 20:54:38 +00:00
move-to-valu-atomicrmw.ll
…
move-to-valu-worklist.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
movreld-bug.ll
…
movrels-bug.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
mubuf-offset-private.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
mubuf-shader-vgpr.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
mubuf.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
mul_int24.ll
…
mul_uint24-amdgcn.ll
AMDGPU: Ignore any_extend in mul24 combine
2018-05-09 21:11:35 +00:00
mul_uint24-r600.ll
…
mul.i16.ll
AMDGPU: Make v4i16/v4f16 legal
2018-06-15 15:15:46 +00:00
mul.ll
[AMDGPU] Fixed some instructions latencies
2018-03-30 16:19:13 +00:00
multi-divergent-exit-region.ll
[AMDGPU] Don't force WQM for DS op
2018-05-07 13:21:26 +00:00
multilevel-break.ll
[AMDGPU] Fixed incorrect break from loop
2018-05-25 07:55:04 +00:00
nested-calls.ll
AMDGPU: Increase default stack alignment
2018-03-29 20:22:04 +00:00
nested-loop-conditions.ll
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.
2018-06-20 22:01:04 +00:00
no-hsa-graphics-shaders.ll
…
no-initializer-constant-addrspace.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
no-shrink-extloads.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
nop-data.ll
…
not-scalarize-volatile-load.ll
…
nullptr.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
omod.ll
…
opencl-image-metadata.ll
…
operand-folding.ll
…
operand-spacing.ll
…
opt-sgpr-to-vgpr-copy.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
optimize-if-exec-masking.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
or.ll
…
over-max-lds-size.ll
…
pack.v2f16.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
pack.v2i16.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
packed-op-sel.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
packetizer.ll
…
parallelandifcollapse.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
parallelorifcollapse.ll
fix typos in comments; NFC
2017-07-16 08:11:56 +00:00
partial-sgpr-to-vgpr-spills.ll
…
partial-shift-shrink.ll
AMDGPU: Handle partial shift reduction for variable shifts
2018-05-09 20:52:54 +00:00
partially-dead-super-register-immediate.ll
…
perfhint.ll
[AMDGPU] Do not consider indirect acces through phi for wave limiter
2018-06-11 16:50:49 +00:00
permute.ll
[AMDGPU] Corrected computeKnownBits for V_PERM_B32
2018-06-13 18:52:54 +00:00
pk_max_f16_literal.ll
[AMDGPU] Truncate packed inline constant
2018-04-24 18:17:55 +00:00
postra-norename.mir
[MachineOperand][Target] MachineOperand::isRenamable semantics changes
2018-02-23 18:25:08 +00:00
predicate-dp4.ll
…
predicates.ll
…
print-mir-custom-pseudo.ll
[CodeGen] Fixed unreachable with -print-machineinstrs and custom pseudo source value
2018-03-27 21:14:04 +00:00
private-access-no-objects.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
private-element-size.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
private-memory-atomics.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
private-memory-r600.ll
AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements
2018-02-16 19:14:17 +00:00
promote-alloca-addrspacecast.ll
…
promote-alloca-array-aggregate.ll
AMDGPU: Fix assert on alloca of array of struct
2017-09-14 18:02:29 +00:00
promote-alloca-array-allocation.ll
…
promote-alloca-bitcast-function.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
promote-alloca-calling-conv.ll
AMDGPU: Increase default stack alignment
2018-03-29 20:22:04 +00:00
promote-alloca-globals.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
promote-alloca-invariant-markers.ll
Rename invariant.group.barrier to launder.invariant.group
2018-05-03 11:03:01 +00:00
promote-alloca-lifetime.ll
…
promote-alloca-mem-intrinsics.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
promote-alloca-no-opts.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
promote-alloca-padding-size-estimate.ll
AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements
2018-02-16 19:14:17 +00:00
promote-alloca-stored-pointer-value.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
promote-alloca-to-lds-icmp.ll
…
promote-alloca-to-lds-phi.ll
…
promote-alloca-to-lds-select.ll
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
promote-alloca-unhandled-intrinsic.ll
…
promote-alloca-volatile.ll
…
pv-packing.ll
…
pv.ll
…
r600-constant-array-fixup.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
r600-encoding.ll
…
r600-export-fix.ll
…
r600-infinite-loop-bug-while-reorganizing-vector.ll
…
r600-legalize-umax-bug.ll
…
r600.alu-limits.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
r600.amdgpu-alias-analysis.ll
[AMDGPU] Update test r600.amdgpu-alias-analysis.ll
2017-11-20 16:53:13 +00:00
r600.bitcast.ll
…
r600.func-alignment.ll
AMDGPU/R600: Make sure functions are cacheline aligned
2018-05-31 04:08:08 +00:00
r600.global_atomics.ll
…
r600.private-memory.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
r600.work-item-intrinsics.ll
[SelectionDAG] Provide adequate register class for RegisterSDNode
2018-02-09 13:55:25 +00:00
r600cfg.ll
…
rcp-pattern.ll
…
read_register.ll
…
read-register-invalid-subtarget.ll
…
read-register-invalid-type-i32.ll
…
read-register-invalid-type-i64.ll
…
readcyclecounter.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
readlane_exec0.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
README
…
reduce-build-vec-ext-to-ext-build-vec.ll
AMDGPU: Make v4i16/v4f16 legal
2018-06-15 15:15:46 +00:00
reduce-load-width-alignment.ll
…
reduce-saveexec.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
reduce-store-width-alignment.ll
AMDGPU: Try a lot harder to emit scalar loads
2018-06-07 09:54:49 +00:00
reduction.ll
AMDGPU: Make v2i16/v2f16 legal on VI
2018-05-22 06:32:10 +00:00
reg-coalescer-sched-crash.ll
…
regcoal-subrange-join-seg.mir
Shrink interval after moving copy in removePartialRedundancy
2018-06-18 17:16:39 +00:00
regcoal-subrange-join.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
regcoalesce-dbg.mir
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
regcoalesce-prune.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
register-count-comments.ll
…
rename-disconnected-bug.ll
…
rename-independent-subregs-mac-operands.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
rename-independent-subregs.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
reorder-stores.ll
…
reqd-work-group-size.ll
AMDGPU: Add pass to optimize reqd_work_group_size
2018-05-18 21:35:00 +00:00
ret_jump.ll
[AMDGPU] fix tests to be independent of FP undef
2018-03-10 16:39:59 +00:00
ret.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
rewrite-out-arguments-address-space.ll
AMDGPU: Look through a bitcast user of an out argument
2017-07-28 19:06:16 +00:00
rewrite-out-arguments.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
rotl.i64.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
rotl.ll
…
rotr.i64.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
rotr.ll
…
rsq.ll
…
rv7x0_count3.ll
…
s_addk_i32.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
s_movk_i32.ll
…
s_mulk_i32.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
sad.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
saddo.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
salu-to-valu.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
sampler-resource-id.ll
…
scalar_to_vector.ll
AMDGPU: Fix scalar_to_vector for v4i16/v4f16
2018-06-20 19:45:48 +00:00
scalar-branch-missing-and-exec.ll
AMDGPU: Bring processors and features in sync with the spec
2018-02-16 21:26:25 +00:00
scalar-store-cache-flush.mir
[AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained.
2018-04-27 17:59:15 +00:00
sched-crash-dbg-value.mir
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
schedule-fs-loop-nested-if.ll
…
schedule-fs-loop-nested.ll
…
schedule-fs-loop.ll
…
schedule-global-loads.ll
…
schedule-if-2.ll
…
schedule-if.ll
…
schedule-ilp.ll
AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
2017-11-20 14:35:53 +00:00
schedule-kernel-arg-loads.ll
[AMDGPU] Prevent post-RA scheduler from breaking memory clauses
2017-09-19 20:54:38 +00:00
schedule-regpressure-limit2.ll
AMDGPU: Replace i64 add/sub lowering
2017-11-15 21:51:43 +00:00
schedule-regpressure-limit3.ll
[AMDGPU] Fix amdgpu-waves-per-eu accounting in scheduler
2018-05-12 01:41:56 +00:00
schedule-regpressure-limit.ll
…
schedule-regpressure.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
schedule-vs-if-nested-loop-failure.ll
…
schedule-vs-if-nested-loop.ll
…
scheduler-subrange-crash.ll
…
scratch-buffer.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
scratch-simple.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
sdiv.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
sdivrem24.ll
…
sdivrem64.ll
[AMDGPU] New 64 bit div/rem expansion
2017-10-06 17:24:45 +00:00
sdwa-gfx9.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
sdwa-peephole-instr.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
sdwa-peephole.ll
AMDGPU: Make v2i16/v2f16 legal on VI
2018-05-22 06:32:10 +00:00
sdwa-preserve.mir
[AMDGPU] Fix the SDWA Peephole phase to handle src for dst:UNUSED_PRESERVE.
2018-03-30 05:03:36 +00:00
sdwa-scalar-ops.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
sdwa-vop2-64bit.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
select64.ll
AMDGPU: Remove -mcpu=SI
2017-08-07 18:30:35 +00:00
select-fabs-fneg-extract-legacy.ll
…
select-fabs-fneg-extract.ll
…
select-i1.ll
AMDGPU: Try a lot harder to emit scalar loads
2018-06-07 09:54:49 +00:00
select-opt.ll
[AMDGPU] Fixed incorrect uniform branch condition
2018-01-09 21:34:43 +00:00
select-vectors.ll
AMDGPU: Make v4i16/v4f16 legal
2018-06-15 15:15:46 +00:00
select.f16.ll
[AMDGPU] Prevent post-RA scheduler from breaking memory clauses
2017-09-19 20:54:38 +00:00
select.ll
…
selectcc-cnd.ll
…
selectcc-cnde-int.ll
…
selectcc-icmp-select-float.ll
…
selectcc-opt.ll
…
selectcc.ll
AMDGPU: Remove -mcpu=SI
2017-08-07 18:30:35 +00:00
selected-stack-object.ll
…
sendmsg-m0-hazard.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
set-dx10.ll
…
setcc64.ll
…
setcc-equivalent.ll
…
setcc-fneg-constant.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
setcc-opt.ll
…
setcc-sext.ll
…
setcc.ll
[DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a canonical manner.
2018-02-23 11:50:42 +00:00
seto.ll
…
setuo.ll
…
sext-eliminate.ll
…
sext-in-reg-failure-r600.ll
…
sext-in-reg.ll
AMDGPU: Try a lot harder to emit scalar loads
2018-06-07 09:54:49 +00:00
sgpr-control-flow.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
sgpr-copy-duplicate-operand.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
sgpr-copy.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
sgprcopies.ll
…
shared-op-cycle.ll
…
shift-and-i64-ubfe.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
shift-and-i128-ubfe.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
shift-i64-opts.ll
…
shl_add_constant.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
shl_add_ptr.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
shl-add-to-add-shl.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
shl.ll
[AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz environment
2017-11-10 02:03:28 +00:00
shl.v2i16.ll
AMDGPU: Try a lot harder to emit scalar loads
2018-06-07 09:54:49 +00:00
shrink-add-sub-constant.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
shrink-carry.mir
[AMDGPU] Shrinking V_SUBBREV_U32
2018-02-24 01:32:32 +00:00
shrink-vop3-carry-out.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
si-annotate-cf-noloop.ll
[AMDGPU] Eliminate no effect instructions before s_endpgm
2017-08-16 04:43:49 +00:00
si-annotate-cf-unreachable.ll
…
si-annotate-cf.ll
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.
2018-06-20 22:01:04 +00:00
si-annotate-cfg-loop-assert.ll
…
si-fix-sgpr-copies.mir
AMDGPU: Don't leave dead illegal VGPR->SGPR copies
2018-03-19 14:07:15 +00:00
si-instr-info-correct-implicit-operands.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
si-lod-bias.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
si-lower-control-flow-kill.ll
AMDGPU: Remove deprecated llvm.AMDGPU.kilp intrinsic
2018-04-24 21:37:57 +00:00
si-lower-control-flow-unreachable-block.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
si-lower-control-flow.mir
[AMDGPU] prevent hitting Assertion `isReg() && "Wrong MachineOperand accessor"'
2018-06-12 00:41:26 +00:00
si-scheduler.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
si-sgpr-spill.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
si-spill-cf.ll
…
si-spill-sgpr-stack.ll
…
si-triv-disjoint-mem-access.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
si-vector-hang.ll
…
sibling-call.ll
[AMDGPU] added writelane intrinsic
2018-02-28 19:10:32 +00:00
sign_extend.ll
AMDGPU: Make v2i16/v2f16 legal on VI
2018-05-22 06:32:10 +00:00
simplify-libcalls.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
simplifydemandedbits-recursion.ll
Use the return value of UpdateNodeOperands(); in some cases, UpdateNodeOperands() modifies the node in-place and using the return value isn’t strictly necessary. However, it does not necessarily modify the node, but may return a resultant node if it already exists in the DAG. See comments in UpdateNodeOperands(). In that case, the return value must be used to avoid such scenarios as an infinite loop (node is assumed to have been updated, so added back to the worklist, and re-processed; however, node hasn’t changed so it is once again passed to UpdateNodeOperands(), assumed modified, added back to worklist; cycle infinitely repeats).
2017-10-16 23:38:53 +00:00
sint_to_fp.f64.ll
…
sint_to_fp.i64.ll
…
sint_to_fp.ll
…
sitofp.f16.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
skip-if-dead.ll
[AMDGPU] fix test to be independent of FP undef
2018-03-09 16:33:34 +00:00
smed3.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
sminmax.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
sminmax.v2i16.ll
AMDGPU: Make v4i16/v4f16 legal
2018-06-15 15:15:46 +00:00
smrd-vccz-bug.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
smrd.ll
AMDGPU: Track physreg uses in SILoadStoreOptimizer
2018-02-23 10:45:56 +00:00
sopk-compares.ll
…
spill-alloc-sgpr-init-bug.ll
AMDGPU: Fix register name format in tests
2018-03-27 18:39:42 +00:00
spill-cfg-position.ll
…
spill-csr-frame-ptr-reg-copy.ll
AMDGPU: Move a flawed assert when spilling SGPRs
2018-04-23 16:13:30 +00:00
spill-empty-live-interval.mir
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
spill-m0.ll
[AMDGPU] Don't force WQM for DS op
2018-05-07 13:21:26 +00:00
spill-scavenge-offset.ll
…
spill-to-smem-m0.ll
…
spill-wide-sgpr.ll
…
split-scalar-i64-add.ll
AMDGPU: Replace i64 add/sub lowering
2017-11-15 21:51:43 +00:00
split-smrd.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
split-vector-memoperand-offsets.ll
…
splitkit.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
sra.ll
[AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz environment
2017-11-10 02:03:28 +00:00
srem.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
srl.ll
…
ssubo.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
stack-realign.ll
AMDGPU: Support realigning stack
2018-03-29 21:30:06 +00:00
stack-size-overflow.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
stack-slot-color-sgpr-vgpr-spills.mir
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
store_typed.ll
…
store-barrier.ll
…
store-global.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
store-hi16.ll
AMDGPU: Add D16 instructions preserve unused bits feature
2018-05-04 20:06:57 +00:00
store-local.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
store-private.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
store-v3i64.ll
…
store-vector-ptrs.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
store-weird-sizes.ll
AMDGPU: Add combine for trunc of bitcast from build_vector
2018-05-09 18:37:39 +00:00
stress-calls.ll
AMDGPU: Add option to stress calls
2017-09-21 07:00:48 +00:00
structurize1.ll
…
structurize.ll
…
sub.i16.ll
AMDGPU: Replace i64 add/sub lowering
2017-11-15 21:51:43 +00:00
sub.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
sub.v2i16.ll
AMDGPU: Make v2i16/v2f16 legal on VI
2018-05-22 06:32:10 +00:00
subreg_interference.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
subreg-coalescer-crash.ll
…
subreg-coalescer-undef-use.ll
AMDGPU: Remove -mcpu=SI
2017-08-07 18:30:35 +00:00
subreg-eliminate-dead.ll
…
subreg-intervals.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
swizzle-export.ll
…
syncscopes.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
tail-call-cgp.ll
AMDGPU: Start adding tail call support
2017-08-11 20:42:08 +00:00
target-cpu.ll
AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements
2018-02-16 19:14:17 +00:00
tex-clause-antidep.ll
…
texture-input-merge.ll
…
trap.ll
AMDGPU: Always set COMPUTE_PGM_RSRC2.ENABLE_TRAP_HANDLER to zero for AMDHSA as
2018-05-29 19:09:13 +00:00
trunc-bitcast-vector.ll
AMDGPU: Fix broken check lines in test
2018-05-08 18:43:44 +00:00
trunc-cmp-constant.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
trunc-combine.ll
AMDGPU: Add combine for trunc of bitcast from build_vector
2018-05-09 18:37:39 +00:00
trunc-store-f64-to-f16.ll
…
trunc-store-i1.ll
…
trunc-store.ll
…
trunc-vector-store-assertion-failure.ll
[AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz environment
2017-11-10 02:03:28 +00:00
trunc.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
tti-unroll-prefs.ll
AMDGPU: Remove -mcpu=SI
2017-08-07 18:30:35 +00:00
twoaddr-mad.mir
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
uaddo.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
udiv.ll
…
udivrem24.ll
…
udivrem64.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
udivrem.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
uint_to_fp.f64.ll
…
uint_to_fp.i64.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
uint_to_fp.ll
…
uitofp.f16.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
umed3.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
unaligned-load-store.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
undefined-physreg-sgpr-spill.mir
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
undefined-subreg-liverange.ll
…
unhandled-loop-condition-assertion.ll
…
uniform-branch-intrinsic-cond.ll
…
uniform-cfg.ll
[AMDGPU] Fixed incorrect uniform branch condition
2018-01-09 21:34:43 +00:00
uniform-crash.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
uniform-loop-inside-nonuniform.ll
[AMDGPU] Revert b0efc4fd6 (https://reviews.llvm.org/D40556)
2018-04-25 12:32:46 +00:00
unify-metadata.ll
…
unigine-liveness-crash.ll
[AMDGPU] fix tests to be independent of FP undef
2018-03-10 16:39:59 +00:00
unknown-processor.ll
[AMDGPU] Change alloca addr space of r600 to 5 for amdgiz environment
2017-11-06 14:32:33 +00:00
unpack-half.ll
[SelectionDAG] Fixed f16-from-vector promotion problem
2018-01-09 21:36:25 +00:00
unroll.ll
…
unsupported-calls.ll
[AMDGPU] Fix assertion due to assuming pointer in default addr space is 32 bit
2017-11-06 13:01:33 +00:00
unsupported-cc.ll
…
urem.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
use-sgpr-multiple-times.ll
AMDGPU: Fix breaking SMEM clauses
2017-11-17 04:18:24 +00:00
usubo.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
v1i64-kernel-arg.ll
…
v_cndmask.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
v_cvt_pk_u8_f32.ll
…
v_mac_f16.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
v_mac.ll
…
v_madak_f16.ll
[AMDGPU] Produce madak and madmk from the two-address pass
2017-09-11 17:13:57 +00:00
valu-i1.ll
[AMDGPU] Fixed incorrect break from loop
2018-05-25 07:55:04 +00:00
vccz-corrupt-bug-workaround.mir
[AMDGPU][Waitcnt] Remove the old waitcnt pass
2018-05-07 14:43:28 +00:00
vector-alloca-addrspacecast.ll
AMDGPU/SI: Don't promote alloca to vector for AddrSpaceCast instruction.
2018-05-11 22:17:57 +00:00
vector-alloca-atomic.ll
AMDGPU/SI: Don't promote alloca to vector for atomic load/store
2018-05-17 21:49:44 +00:00
vector-alloca.ll
[AMDGPU] Fix pointer info for pseudo source for r600
2017-11-10 01:53:24 +00:00
vector-extract-insert.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
vector-legalizer-divergence.ll
[CodeGen] Always update divergence in SelectionDAG::UpdateNodeOperands
2018-06-04 20:19:45 +00:00
vectorize-global-local.ll
…
vertex-fetch-encoding.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
vgpr-spill-emergency-stack-slot-compute.ll
CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT/SplitVecRes_INSERT_VECTOR_ELT
2017-12-02 22:13:22 +00:00
vgpr-spill-emergency-stack-slot.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
vi-removed-intrinsics.ll
…
vop-shrink-frame-index.mir
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
vop-shrink-non-ssa.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vop-shrink.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
vselect64.ll
…
vselect.ll
…
vtx-fetch-branch.ll
…
vtx-schedule.ll
…
wait.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
waitcnt-back-edge-loop.mir
[AMDGPU][Waitcnt] Fix handling of loops with many bottom blocks
2018-05-30 15:47:45 +00:00
waitcnt-debug.mir
[AMDGPU] Waitcnt pass: add debug options
2018-04-25 19:21:26 +00:00
waitcnt-flat.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
waitcnt-loop-single-basic-block.mir
[AMDGPU] Waitcnt pass: Modify the waitcnt pass to propagate info in the case of a single basic block loop. mergeInputScoreBrackets() does this for us; update it so that it processes the single bb's score bracket when processing the single bb's preds. It is, after all, a pred of itself, so it's score bracket is needed.
2018-03-14 22:04:32 +00:00
waitcnt-looptest.ll
[AMDGPU] Increased vector length for global/constant loads.
2018-03-07 17:09:18 +00:00
waitcnt-no-redundant.mir
[AMDGPU] Make note of existing waitcnt instrs; this is add-on work related to suppression of redundant waitcnt instrs. It is necessary to make note of these existing waitcnt instrs so that we do not fall into an infinite loop when handling loops. Also, [NFC] some minor code clean-up.
2018-02-19 19:19:59 +00:00
waitcnt-permute.mir
[AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained.
2018-04-27 17:59:15 +00:00
waitcnt.mir
[AMDGPU][Waitcnt] Fix handling of flat instrs
2018-06-04 16:51:59 +00:00
wave_dispatch_regs.ll
[AMDGPU] Ensure there are enough registers for wave dispatch
2018-04-11 17:18:36 +00:00
widen_extending_scalar_loads.ll
AMDGPU: Preserve metadata when widening loads
2018-06-05 19:52:56 +00:00
widen-smrd-loads.ll
AMDGPU: Try a lot harder to emit scalar loads
2018-06-07 09:54:49 +00:00
widen-vselect-and-mask.ll
DAG: Fix creating select with wrong condition type
2017-10-25 07:14:07 +00:00
wqm.ll
[AMDGPU] Fixed WWM bug in block otherwise entirely in WQM
2018-05-27 17:26:11 +00:00
wqm.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
write_register.ll
[AMDGPU] Eliminate no effect instructions before s_endpgm
2017-08-16 04:43:49 +00:00
write-register-vgpr-into-sgpr.ll
[AMDGPU] Eliminate no effect instructions before s_endpgm
2017-08-16 04:43:49 +00:00
wrong-transalu-pos-fix.ll
…
xfail.r600.bitcast.ll
…
xnor.ll
[AMDGPU] Fixed incorrect -mcpu=gfx800 in xnor.ll test. NFC.
2018-05-31 19:39:54 +00:00
xor.ll
…
zero_extend.ll
…
zext-i64-bit-operand.ll
…
zext-lid.ll
AMDGPU: Fix default range in non-kernel functions
2017-10-23 17:09:35 +00:00

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.
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